Patents by Inventor Narbeh Derhacobian

Narbeh Derhacobian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446747
    Abstract: A method can include, by operation of a controller circuit, writing data into a volatile memory portion formed in an integrated circuit substrate of a memory device. In response to first conditions, date can be written from the volatile memory portion into a nonvolatile memory portion formed in the same integrated circuit substrate as the volatile memory portion. The nonvolatile memory portion can store the data in two terminal memory elements re-programmable between at least two different resistance states.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 15, 2019
    Assignee: Adesto Technology Corporation
    Inventors: Narbeh Derhacobian, Shane Charles Hollmer
  • Patent number: 9570166
    Abstract: A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: February 14, 2017
    Assignee: Adesto Technologies Corporation
    Inventors: Nad Edward Gilbert, Ishai Naveh, Narbeh Derhacobian
  • Patent number: 9159414
    Abstract: An integrated circuit may can include a memory section that stores data in programmable impedance elements arranged at cross points of select lines and sub bit lines, groups of sub bit lines each being connected to a different main bit line, the elements being formed above a substrate surface.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: October 13, 2015
    Assignee: Adesto Technologies Corporation
    Inventors: Narbeh Derhacobian, Shane Charles Hollmer, John Dinh
  • Patent number: 9007814
    Abstract: An integrated circuit (IC) device can include a plurality of memory cells with programmable impedance elements. A circuit can be configured to read a data value stored by an element of a memory cell by application of at least one read voltage pulse and at least one relaxation voltage pulse across the terminals of the element; wherein the read voltage pulse has a same polarity as a voltage used to program the element, the relaxation voltage pulse has a different polarity than the read voltage pulse, and neither the read or relaxation voltage pulses program the element to a particular impedance state.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: April 14, 2015
    Assignee: Adesto Technologies Corporation
    Inventor: Narbeh Derhacobian
  • Patent number: 8995173
    Abstract: A memory device can include a plurality of memory cells, each including a dynamic section configured to store data dynamically, and a programmable impedance section comprising at least one programmable element programmable between at least two different data states, the programmable impedance section configured to establish a data value stored by the dynamic section in response to a recall signal.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: March 31, 2015
    Assignee: Adesto Technologies Corporation
    Inventor: Narbeh Derhacobian
  • Patent number: 8947913
    Abstract: Integrated circuit (IC) devices are disclosed that include programmable impedance elements (elements) as data storage element. In some embodiments, IC devices can include latch circuit with one or more elements that establish a function of an associated circuit. In other embodiments, IC devices can include elements arranged in a cross-point array connected to control terminals of access devices. In still other embodiments, a memory device can include a programmable address decoder. Corresponding methods are also disclosed.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: February 3, 2015
    Assignee: Adesto Technologies Corporation
    Inventors: Narbeh Derhacobian, Ishai Naveh
  • Patent number: 8913444
    Abstract: A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element. In other embodiments, a memory device can include both standard and strong read operations, where strong read operations apply more energy to a selected memory element than a standard read operation.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: December 16, 2014
    Assignee: Adesto Technologies Corporation
    Inventors: Nad Edward Gilbert, Ishai Naveh, Narbeh Derhacobian
  • Patent number: 8822967
    Abstract: Phase change devices, particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. Structure allows application in which an electrical connection can be created between two active terminals, with control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals, allowing use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. Programming control can be placed outside of main signal path through the phase change device, reducing impact of associated capacitance and resistance of the device.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: September 2, 2014
    Assignee: Agate Logic, Inc.
    Inventors: Louis Charles Kordus, II, Antonietta Oliva, Narbeh Derhacobian, Vei-Han Chan
  • Patent number: 8687403
    Abstract: An integrated circuit (IC) device may include a first portion having a plurality of volatile memory cells; and a second portion coupled by a data transfer path to the first portion, the second portion including a plurality of nonvolatile memory cells, each nonvolatile memory cell including at least one resistive element programmable more than once between different resistance values. A memory device may also include variable impedance elements accessible by access bipolar junction transistors (BJTs) having at least a portion formed by a semiconductor layer formed over a substrate. A memory device may also include a plurality of memory elements that each includes a dielectric layer formed between a first and second electrode, the dielectric layer including a solid electrolyte with a soluble metal having a mobility less than that of silver in a germanium disulfide.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: April 1, 2014
    Assignee: Adesto Technologies Corporation
    Inventors: Narbeh Derhacobian, Shane Charles Hollmer, Ishai Naveh
  • Patent number: 8675396
    Abstract: An integrated circuit (IC) device can include a memory array having memory elements formed with a solid ion conductor, the memory array programmable to provide portions with different response types; and a logic section comprising logic circuits configured to perform logic functions, the logic section being coupled to the memory array to store and read data values therefrom. A memory device can also have a plurality of access ports, each configurable to access any of the different portions of the memory array. A memory device can further include a read circuit configured to read data values from the different portions according to the response type of each portion.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: March 18, 2014
    Assignee: Adesto Technologies Corporation
    Inventors: Narbeh Derhacobian, Ishai Naveh, Shane Charles Hollmer
  • Patent number: 8659926
    Abstract: Methods and circuits for CAM cells using PMCs are disclosed herein. In one embodiment, a BCAM cell can include: (i) a first PMC coupled to a first access transistor and a bit node, where the first access transistor is coupled to a true bit line; (ii) a second PMC cell coupled to a second access transistor and the bit node, where the second access transistor is coupled to a complement bit line, and the first and second access transistors are controllable by a word line; (iii) a program enable transistor coupled to the bit node, and configured to couple a program control voltage to the bit node when enabled; and (iv) a match indication transistor configured to discharge a match line in response to states of the true and complement bit lines relative to the bit node.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: February 25, 2014
    Assignee: Adesto Technologies Corporation
    Inventor: Narbeh Derhacobian
  • Patent number: 8331128
    Abstract: A memory device may include a plurality of memory cells each having elements with at least one solid ion conductor programmable between at least two different impedance states for at least two different data retention times, the plurality of memory cells being dividable into a plurality of portions, each portion being separately configurable for one of the data retention times.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: December 11, 2012
    Assignee: Adesto Technologies Corporation
    Inventors: Narbeh Derhacobian, Shane Charles Hollmer
  • Patent number: 8320148
    Abstract: Methods and circuits for CAM cells using PMCs are disclosed herein. In one embodiment, a BCAM cell can include: (i) a first PMC coupled to a first access transistor and a bit node, where the first access transistor is coupled to a true bit line; (ii) a second PMC cell coupled to a second access transistor and the bit node, where the second access transistor is coupled to a complement bit line, and the first and second access transistors are controllable by a word line; (iii) a program enable transistor coupled to the bit node, and configured to couple a program control voltage to the bit node when enabled; and (iv) a match indication transistor configured to discharge a match line in response to states of the true and complement bit lines relative to the bit node.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: November 27, 2012
    Assignee: Adesto Technologies Corporation
    Inventor: Narbeh Derhacobian
  • Patent number: 8294488
    Abstract: An integrated circuit may include a plurality of sub bit line groups, each sub bit line group coupled to a different main bit line by a corresponding access device; and a plurality of programmable impedance elements arranged into element groups, each element group being coupled to a corresponding each sub bit line.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: October 23, 2012
    Assignee: Adesto Technologies Corporation
    Inventors: Narbeh Derhacobian, Shane Charles Hollmer, John Dinh
  • Publication number: 20120182794
    Abstract: Phase change devices, particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. Structure allows application in which an electrical connection can be created between two active terminals, with control of the connection being effected using a separate terminal or terminals Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals, allowing use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. Programming control can be placed outside of main signal path through the phase change device, reducing impact of associated capacitance and resistance of the device.
    Type: Application
    Filed: March 28, 2012
    Publication date: July 19, 2012
    Applicant: Agate Logic Inc.
    Inventors: Louis Charles Kordus, II, Antonietta Oliva, Narbeh Derhacobian, Vei-Han Chan
  • Patent number: 8183551
    Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: May 22, 2012
    Assignee: Agale Logic, Inc.
    Inventors: Louis Charles Kordus, II, Antonietta Oliva, Narbeh Derhacobian, Vei-Han Chan
  • Patent number: 7755389
    Abstract: Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: July 13, 2010
    Assignee: Agate Logic, Inc.
    Inventors: Colin Neal Murphy, Narbeh Derhacobian, Louis Charles Kordus, II, Antonietta Oliva, Vei-Han Chan, Thomas E. Stewart, Jr.
  • Publication number: 20090134910
    Abstract: Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.
    Type: Application
    Filed: January 7, 2009
    Publication date: May 28, 2009
    Inventors: Colin Neal Murphy, Narbeh Derhacobian, Louis Charles Kordus, II, Antonietta Oliva, Vei-Han Chan, Thomas E. Stewart, JR.
  • Publication number: 20080206922
    Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device.
    Type: Application
    Filed: May 7, 2008
    Publication date: August 28, 2008
    Inventors: Antonietta Oliva, Louis Charles Kordus, Narbeh Derhacobian, Vei-Han Chan, Thomas E. Stewart
  • Publication number: 20080025080
    Abstract: Methods and apparatus for programming a phase change device (PCD) to a low resistance state. According to an exemplary method, one or more first programming pulses having a predetermined magnitude and/or duration are applied to a PCD. After each programming pulse is applied, the programmed resistance of the PCD is compared to a target resistance specification. If the programmed resistance is not in accordance with the target resistance specification, one or more second programming pulses having a magnitude and/or duration different than the magnitude and/or duration of the one or more first programming pulses are applied to the PCD. This process is repeated until the programmed resistance of the PCD satisfies the target resistance specification or it is determined that the PCD cannot be programmed to a resistance value that satisfies the target resistance specification.
    Type: Application
    Filed: July 27, 2006
    Publication date: January 31, 2008
    Inventors: Vei-Han Chan, Louis Kordus, Narbeh Derhacobian, Jason Golbus