Abstract: Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.

Abstract: A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.

Abstract: One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.

Abstract: One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

Abstract: One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.

Abstract: A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.

Abstract: A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region and applying a third voltage that is constant and negative to the substrate so that the effect of spillover electrons is substantially reduced when compared with when the third constant voltage is absent.

Abstract: A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase pulse, the erase verify routine is performed on all the IO's together. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. This erase pulse that provides a substantially high electric field is selected to erase band to band currents for the entire array that are larger than can be supplied by drain pumps.

Abstract: One aspect of the present invention relates to a non-volatile semiconductor memory device, containing a substrate, the substrate having a core region and a periphery region; a charge trapping dielectric over the core region of the substrate; a gate dielectric in the periphery region of the substrate; buried bitlines under the charge trapping dielectric in the core region; and wordlines over the charge trapping dielectric in the core region, wherein the core region is substantially planar.

Abstract: An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using an initial negative gate erase voltage to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. By utilizing a negative gate erase voltage, the cell does not require increased erase time to reduce the cell threshold and avoid incomplete erase conditions as the number of program-erase cycles increases.

Abstract: A high voltage transistor exhibiting low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a field implant blocking mask over the channel area, thereby producing a transistor with low body effect, the field implant blocking mask having appropriate openings so that the field implant occurs at the edges of the channel, thereby reducing leakage.

Abstract: A method for reducing processing steps when fabricating a flash memory array comprising a core area and a periphery area having high-voltage transistors is disclosed. The method includes the steps of depositing a layer of type-2 polysilicon and mask, and selectively etching the type-2 polysilicon. The method further includes the steps of performing a blank implant before removal of the mask over both the core area and the periphery area, wherein deposition of a high-voltage implant mask but is unnecessary. In a preferred embodiment, a NAND flash memory array is fabricated and the blank implant comprises phosphorus at a dose of approximately 3×1012 cm−2 at 30 keV.

Abstract: An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure having charge stored near both the source and drain. During the erase operation, a negative gate erase voltage is applied along with a positive source and drain voltage to improve the speed of erase operations and performance of the non-volatile memory cell after many program-erase cycles.

Abstract: A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

Abstract: A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes: applying a voltage across the gate and the first region in accordance with a coarse erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region; and applying a voltage across the gate and the first region in accordance with a fine erase sequence of voltages so that a portion of the first amount of charge is removed from the charge trapping region.

Abstract: A method of erasing a memory cell that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes simultaneously applying a first positive voltage across the gate and a second positive voltage to the first region, wherein the second positive voltage is greater than the first positive voltage.

Abstract: A voltage control circuit that narrows the distribution of threshold voltages of memory cells by using nonlinearly incremented programming voltages. To do so, the voltage control circuit applies to the memory cells a first program pulse of a first voltage, a second program pulse of a second voltage to the memory cell, and a third program pulse of a third voltage, where the difference between the third voltage and the second voltage is less than the difference between the second voltage and the first voltage.

Abstract: A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire array are larger than can be supplied by drain pumps. After the first erase pulse, the erase verify routine can be performed on all the IO's together. In one particular example, a Vdrain voltage is selected to be at a substantially high positive voltage and the value of Vgate voltage is at a substantially high negative voltage where the voltage potential between Vdrain and Vgate is also a substantially high voltage.

Abstract: A memory cell that includes a substrate that has a first region and a second region with a channel therebetween, wherein the first region generates hot carriers. The memory cell further includes a gate above the channel and a charge trapping region that contains a first amount of charge. A current limiter that limits the number of the generated hot carriers that can flow into the channel, wherein the current limiter does not control the voltage of the second region.

Abstract: A programming and erase method that extends erase time degradation of nonvolatile memory devices by using a constant erase voltage and a set of program voltages, where the average program voltage of the set of the program voltages is approximately equal to the constant erase voltage.