Abstract: Devices, methods, and systems for managing temperature dependent failures in a memory device. An erase failure of a memory block is detected, and marked as a grown bad block if the memory device temperature is below a threshold temperature. If the temperature exceeds the threshold temperature, it is determined whether memory cells of the block exceed a first threshold voltage. If the memory cells of the block exceed the first threshold voltage, the block is marked as a potential grown bad block. If the memory cells of the block are below the first threshold voltage, it is determined whether a number of the memory cells of the block exceed a second threshold voltage. If the memory cells of the block are below the second threshold, the block is programmed. If the memory cells of the block exceed the second threshold, the block is marked for error correction and programmed.

Abstract: Devices, methods, and systems for managing temperature dependent failures in a memory device. An erase failure of a memory block is detected, and marked as a grown bad block if the memory device temperature is below a threshold temperature. If the temperature exceeds the threshold temperature, it is determined whether memory cells of the block exceed a first threshold voltage. If the memory cells of the block exceed the first threshold voltage, the block is marked as a potential grown bad block. If the memory cells of the block are below the first threshold voltage, it is determined whether a number of the memory cells of the block exceed a second threshold voltage. If the memory cells of the block are below the second threshold, the block is programmed. If the memory cells of the block exceed the second threshold, the block is marked for error correction and programmed.

Abstract: Apparatuses and techniques are described for more efficiently allocating blocks of data in a memory device. The number of dedicated single-level cell (SLC) blocks which are allocated at the time of manufacture of a memory device can be reduced by transitioning a portion of the multi-level cell (MLC) blocks to an SLC mode at various times in the lifetime of the memory device. In one approach, separate counts are maintained for an MLC block in the SLC and MLC modes. The separate counts can be used to select an MLC block to transition to the SLC mode, or to select an MLC block to program. In another approach, a single count is maintained, where the SLC cycles are weighted less heavily than the MLC cycles.

Abstract: Apparatuses and techniques are described for more efficiently allocating blocks of data in a memory device. The number of dedicated single-level cell (SLC) blocks which are allocated at the time of manufacture of a memory device can be reduced by transitioning a portion of the multi-level cell (MLC) blocks to an SLC mode at various times in the lifetime of the memory device. In one approach, separate counts are maintained for an MLC block in the SLC and MLC modes. The separate counts can be used to select an MLC block to transition to the SLC mode, or to select an MLC block to program. In another approach, a single count is maintained, where the SLC cycles are weighted less heavily than the MLC cycles.

Abstract: A storage system and method for improving read performance using multiple copies of a logical-to-physical address table are provided. In one embodiment, a method for parallelism is provided that is performed in a storage system comprising a plurality of memory areas accessible in parallel, wherein each memory area stores a copy of a logical-to-physical address table. The method comprises reading portions of the logical-to-physical address tables in parallel from the plurality of memory areas, wherein the portions comprise translations for logical addresses associated with a plurality of memory commands; translating the logical addresses associated with the plurality of memory commands into physical addresses using the read portions; and performing the plurality of memory commands. Other embodiments are provided.

Abstract: A storage system and method for improving read performance using multiple copies of a logical-to-physical address table are provided. In one embodiment, a method for parallelism is provided that is performed in a storage system comprising a plurality of memory areas accessible in parallel, wherein each memory area stores a copy of a logical-to-physical address table. The method comprises reading portions of the logical-to-physical address tables in parallel from the plurality of memory areas, wherein the portions comprise translations for logical addresses associated with a plurality of memory commands; translating the logical addresses associated with the plurality of memory commands into physical addresses using the read portions; and performing the plurality of memory commands. Other embodiments are provided.

Abstract: A storage system and method for executing file-based firmware commands and collecting response data are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: receive a request from a host in communication with the storage system to write data in a file, wherein the file is identified by a file path name; determine whether the file path name matches a predetermined file path name; in response to determining that the file path name does not match the predetermined file path name, write the data in the file; and in response to determining that the file path name matches the predetermined file path name, execute a command represented by the data. Other embodiments are provided.

Abstract: A memory system may be configured to perform immediate folding of data from a low storage density area to a high storage density area. A low storage density target area may be monitored, and when a capacity of the low storage density target area reaches a threshold level, data stored in the low storage density target area may be folded to an associated high storage density target area. The memory system may utilize a pointer system to manage the folding of data. The pointer system may also be utilized for read operations in order to avoid updating address mapping tables for both the low storage density and the high storage density areas.

Abstract: A storage system and method for executing file-based firmware commands and collecting response data are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: receive a request from a host in communication with the storage system to write data in a file, wherein the file is identified by a file path name; determine whether the file path name matches a predetermined file path name; in response to determining that the file path name does not match the predetermined file path name, write the data in the file; and in response to determining that the file path name matches the predetermined file path name, execute a command represented by the data. Other embodiments are provided.

Abstract: In a multi-plane non-volatile memory, good blocks of different planes are linked for parallel operation for storing long host writes. Where bad blocks in one or more planes result in unlinked blocks, the unlinked blocks are configured for individual operation to store short host writes and/or memory system management data. Unlinked blocks may be configured as Single Level Cell (SLC) blocks while linked blocks may be configured as SLC blocks or Multi Level Cell (MLC) blocks.

Abstract: A memory system may be configured to perform immediate folding of data from a low storage density area to a high storage density area. A low storage density target area may be monitored, and when a capacity of the low storage density target area reaches a threshold level, data stored in the low storage density target area may be folded to an associated high storage density target area. The memory system may utilize a pointer system to manage the folding of data. The pointer system may also be utilized for read operations in order to avoid updating address mapping tables for both the low storage density and the high storage density areas.

Abstract: A non-volatile memory system may include a plurality of dies, where the plurality of dies are configured in a plurality of chip enable groups and at least one of the chip enable groups includes less than a maximum number of dies that may be uniquely identified according to a die selection scheme, where different memory arrays have different capacities and/or include memory elements of different types or technologies, or some combination thereof. One or more virtual die layouts, addressing schemes and mappings, wear leveling schemes, and initialization schemes may be employed for these multi-die configurations.

Abstract: A non-volatile memory system may include a plurality of memory dies and a controller that is configured to write data into the memory dies according to a multi-die interleave scheme. A total number of the dies may be a non-multiple of a die component number of the interleave scheme. The controller may select abstract address based on a virtual die layout, and translate the abstract address to actual physical addresses. The translation may identify actual blocks located in different rows of blocks. The controller may also read data sets from the memory dies. To do so, the controller may translate an abstract address to actual physical addresses, which may similarly identify actual blocks located in different rows of blocks.

Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an error correction coding (ECC) decoder. The non-volatile memory is configured to sense hard bit data and soft bit data corresponding to multiple ECC codewords from a word line of the non-volatile memory and to sense soft bit data for the multiple ECC codewords. The soft bit data includes sub codes for each of the multiple ECC codewords. The non-volatile memory is configured to send less than all of the sensed soft bit sub codes to the ECC decoder.

Abstract: A storage device with a memory may improve yield by reducing the allocation of blocks for secondary writes in a dual programming system. In a dual programming system, all host writes are written to both a primary copy and to a secondary copy. If the secondary copy blocks that are available have a higher endurance, then the overall allocation of available blocks for use as a secondary copy block can be reduced (improving yield). In one embodiment, utilizing different trim parameters for the secondary copy blocks may be used to increase the endurance for those blocks. Before programming the secondary copy, the trim parameters may be adjusted to increase endurance and after programming the secondary copy, the trim parameters may be adjusted back to the default value that is used when programming the primary copy.

Abstract: A non-volatile memory system may include detection circuitry configured to detect that a host system is configured to initially communicate a clock signal and initialization command signals at a voltage level lower than its input/output driver circuit is configured to receive the signals. In response to the detection, the detection circuitry may switch a regulator circuit from a high voltage mode to a low voltage mode so that the input/output driver circuit is ready to receive the initialization commands at the lower voltage level.

Abstract: A memory system or flash card may include an algorithm for identifying and accounting for the rewrite frequency of data to be written to the card. The file system partition or file type of data may be used for monitoring rewrite frequency and predicting future rewrites. A learning algorithm that monitors rewrites may be implemented in firmware for accurate and dynamic identification of file types/partitions with the most likely rewrites. The identification of rewrites may be used to sort the data into groups (e.g. hot data=likely rewritten, and cold data=not likely to be rewritten). The hot data may stay in single level cell (SLC) update blocks longer, while the cold data can be moved to MLC blocks sooner.

Abstract: A non-volatile memory system may include a plurality of memory dies and a controller that is configured to write data into the memory dies according to a multi-die interleave scheme. A total number of the dies may be a non-multiple of a die component number of the interleave scheme. The controller may select abstract address based on a virtual die layout, and translate the abstract address to actual physical addresses. The translation may identify actual blocks located in different rows of blocks. The controller may also read data sets from the memory dies. To do so, the controller may translate an abstract address to actual physical addresses, which may similarly identify actual blocks located in different rows of blocks.

Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an error correction coding (ECC) decoder. The non-volatile memory is configured to sense hard bit data and soft bit data corresponding to multiple ECC codewords from a word line of the non-volatile memory and to sense soft bit data for the multiple ECC codewords. The soft bit data includes sub codes for each of the multiple ECC codewords. The non-volatile memory is configured to send less than all of the sensed soft bit sub codes to the ECC decoder.

Abstract: A storage device with a memory may improve yield by reducing the allocation of blocks for secondary writes in a dual programming system. In a dual programming system, all host writes are written to both a primary copy and to a secondary copy. If the secondary copy blocks that are available have a higher endurance, then the overall allocation of available blocks for use as a secondary copy block can be reduced (improving yield). In one embodiment, utilizing different trim parameters for the secondary copy blocks may be used to increase the endurance for those blocks. Before programming the secondary copy, the trim parameters may be adjusted to increase endurance and after programming the secondary copy, the trim parameters may be adjusted back to the default value that is used when programming the primary copy.