Abstract: A data storage device may include a memory die. The memory die may include a memory. A method may include selecting a source compaction block of the memory for a compaction process. The source compaction block stores data. The method may further include writing the data to a destination compaction block of the memory at a rate that is based on a number of multiple blocks of the memory associated with the compaction process.

Abstract: A non-volatile memory system may include a plurality of dies, where the plurality of dies are configured in a plurality of chip enable groups and at least one of the chip enable groups includes less than a maximum number of dies that may be uniquely identified according to a die selection scheme, where different memory arrays have different capacities and/or include memory elements of different types or technologies, or some combination thereof. One or more virtual die layouts, addressing schemes and mappings, wear leveling schemes, and initialization schemes may be employed for these multi-die configurations.

Abstract: A non-volatile memory system may include detection circuitry configured to detect that a host system is configured to initially communicate a clock signal and initialization command signals at a voltage level lower than its input/output driver circuit is configured to receive the signals. In response to the detection, the detection circuitry may switch a regulator circuit from a high voltage mode to a low voltage mode so that the input/output driver circuit is ready to receive the initialization commands at the lower voltage level.

Abstract: A method of operating a data storage device having a memory includes scheduling a first operation to be performed at one or more memory dies of a first meta plane of a plurality of meta planes of the memory. The first operation is to be performed during a particular time period. The method also includes determining that performance of the first operation consumes less than a threshold amount of power. The method further includes scheduling a second operation to be performed at one or more memory dies of a second meta plane of the plurality of meta planes, or at one of the dies in the same meta plane, during the particular time period and performing the first operation concurrently with the second operation. A peak amount of power corresponding to concurrent execution of the first operation and the second operation is less than the threshold amount of power.

Abstract: Systems and method for performing intelligent flash management are disclosed. A controller may determine if a write pattern exists between a set of writes associated with a first data chunk and a set of writes associated with a second data chunk based on whether a number of writes for first data chunk is equal to a number of writes for second data chunk; a degree to which a sequence of logical block address for the first data chunk matches the sequence of logical block addresses for the second data chunk; and a degree to which a size of each write for the first data chunk matches a size of each write for the second data chunk. The controller may then perform storage management operations based on whether or not a write pattern exists.

Abstract: A data storage device may include a memory die. The memory die may include a memory. A method may include selecting a source compaction block of the memory for a compaction process. The source compaction block stores data. The method may further include writing the data to a destination compaction block of the memory at a rate that is based on a number of multiple blocks of the memory associated with the compaction process.

Abstract: In a multi-plane non-volatile memory, good blocks of different planes are linked for parallel operation for storing long host writes. Where bad blocks in one or more planes result in unlinked blocks, the unlinked blocks are configured for individual operation to store short host writes and/or memory system management data. Unlinked blocks may be configured as Single Level Cell (SLC) blocks while linked blocks may be configured as SLC blocks or Multi Level Cell (MLC) blocks.

Abstract: A method for optimizing a boot up sequence includes, during a host idle time or during data transfer: obtaining a predicted read address from the a prediction table, prefetching from the non-volatile data store, and saving the prefetched data in memory. Also included is receiving a current read command issued by the host and if the read address matches the predicted read address, providing to the host the prefetched data saved in temporary memory, and indicating a match. If a match is not indicated, obtaining current data from the non-volatile data store corresponding to the read address of the current read command, and providing the current data to the host. If a match was not indicated, searching the data prediction table for the predicted read address that matches the read address corresponding to the current read command, and if found in the data prediction table, recording the offset value.

Abstract: A memory system or flash card may include an algorithm for identifying a pattern in a sustained or continuous write operation. In one example, a video recording device may be a host that continuously writes data to a memory card in an identifiable pattern. The pattern identification algorithm may be stored in the firmware of the memory card and used to schedule background operations during the predicted idle times in which the host is not writing data to the memory card.

Abstract: A memory system or flash card may include an algorithm for identifying and accounting for the rewrite frequency of data to be written to the card. The file system partition or file type of data may be used for monitoring rewrite frequency and predicting future rewrites. A learning algorithm that monitors rewrites may be implemented in firmware for accurate and dynamic identification of file types/partitions with the most likely rewrites. The identification of rewrites may be used to sort the data into groups (e.g. hot data=likely rewritten, and cold data=not likely to be rewritten). The hot data may stay in single level cell (SLC) update blocks longer, while the cold data can be moved to MLC blocks sooner.

Abstract: A method for optimizing a boot up sequence includes, during a host idle time or during data transfer: obtaining a predicted read address from the a prediction table, prefetching from the non-volatile data store, and saving the prefetched data in memory. Also included is receiving a current read command issued by the host and if the read address matches the predicted read address, providing to the host the prefetched data saved in temporary memory, and indicating a match. If a match is not indicated, obtaining current data from the non-volatile data store corresponding to the read address of the current read command, and providing the current data to the host. If a match was not indicated, searching the data prediction table for the predicted read address that matches the read address corresponding to the current read command, and if found in the data prediction table, recording the offset value.

Abstract: Systems and method for performing intelligent flash management are disclosed. A controller may determine if a write pattern exists between a set of writes associated with a first data chunk and a set of writes associated with a second data chunk based on whether a number of writes for first data chunk is equal to a number of writes for second data chunk; a degree to which a sequence of logical block address for the first data chunk matches the sequence of logical block addresses for the second data chunk; and a degree to which a size of each write for the first data chunk matches a size of each write for the second data chunk. The controller may then perform storage management operations based on whether or not a write pattern exists.

Abstract: A memory system or flash card may include an algorithm for identifying a pattern in a sustained or continuous write operation. In one example, a video recording device may be a host that continuously writes data to a memory card in an identifiable pattern. The pattern identification algorithm may be stored in the firmware of the memory card and used to schedule background operations during the predicted idle times in which the host is not writing data to the memory card.