Patents by Inventor Naresh Nayar
Naresh Nayar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10649853Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: August 21, 2018Date of Patent: May 12, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10613940Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: November 7, 2017Date of Patent: April 7, 2020Assignee: International Business Machines CorporationInventors: Guy Lynn Gutherie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10545837Abstract: An approach is provided in which an Infrastructure as a Service (IaaS) system is established in a cloud that includes a plurality of virtual machines. Each of the plurality of virtual machines are allocated to one or more of a plurality of datastores based on one or more user inputs. Next, one of a plurality of priorities are assigned to each of the plurality of virtual machines based on the one or more of the plurality of datastores to which each of the plurality of virtual machines is allocated. In turn, the virtual machines are recovered in the cloud in an order determined, at least in part, by their assigned one of the plurality of priorities.Type: GrantFiled: February 20, 2018Date of Patent: January 28, 2020Assignee: International Business Machines CorporationInventors: Josep Cors, Naresh Nayar, Birgit M. Pfitzmann, Oliver Raff
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Publication number: 20190258551Abstract: An approach is provided in which an Infrastructure as a Service (IaaS) system is established in a cloud that includes a plurality of virtual machines. Each of the plurality of virtual machines are allocated to one or more of a plurality of datastores based on one or more user inputs. Next, one of a plurality of priorities are assigned to each of the plurality of virtual machines based on the one or more of the plurality of datastores to which each of the plurality of virtual machines is allocated. In turn, the virtual machines are recovered in the cloud in an order determined, at least in part, by their assigned one of the plurality of priorities.Type: ApplicationFiled: February 20, 2018Publication date: August 22, 2019Inventors: Josep Cors, Naresh Nayar, Birgit M. Pfitzmann, Oliver Raff
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Patent number: 10354085Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.Type: GrantFiled: December 29, 2017Date of Patent: July 16, 2019Assignee: International Business Machines CorporationInventors: Giles R. Frazier, Bruce Mealey, Naresh Nayar
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Patent number: 10346255Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: August 22, 2018Date of Patent: July 9, 2019Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10339009Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: August 22, 2018Date of Patent: July 2, 2019Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10223218Abstract: A mechanism is provided for disaster recovery of managed systems. Responsive to an identification of a virtual machine recovery condition occurring at a first node site, one or more virtual machines to be recovered to a second site node are identified. Further responsive to the identification of the virtual machine recovery condition occurring at the first node site and responsive to the identification of the one or more virtual machines to be recovered, at least some of records/metadata state data associated with the one or more virtual machines are transmitted to the second site node.Type: GrantFiled: November 29, 2016Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Josep Cors, Richard E. Harper, Naresh Nayar, Gerhard A. Widmayer
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Publication number: 20190004902Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: ApplicationFiled: August 21, 2018Publication date: January 3, 2019Inventors: GUY LYNN GUTHRIE, NARESH NAYAR, GERAINT NORTH, HUGH SHEN, WILLIAM STARKE, PHILLIP WILLIAMS
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Patent number: 10171315Abstract: A method to generate an executable orchestration process includes: querying a user to enter first computer code for activating a service; querying the user to enter second computer code for undoing actions performed in the activating; loading pre-defined third computer code for determining whether the activated service is a success or has an error, based on the service; loading pre-defined fourth computer code for correcting the error; generating an executable orchestration function from the first through fourth computer code; and generating the orchestration process from the executable orchestration function.Type: GrantFiled: June 29, 2016Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robin C. Arnold, Thomas E. Chefalas, Florian D. Graf, Andrzej Kochut, Naresh Nayar, Birgit M. Pfitzmann, Mahesh Viswanathan
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Publication number: 20180357131Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: ApplicationFiled: August 22, 2018Publication date: December 13, 2018Inventors: GUY LYNN GUTHRIE, NARESH NAYAR, GERAINT NORTH, HUGH SHEN, WILLIAM STARKE, PHILLIP WILLIAMS
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Publication number: 20180357129Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: ApplicationFiled: August 22, 2018Publication date: December 13, 2018Inventors: GUY LYNN GUTHRIE, NARESH NAYAR, GERAINT NORTH, HUGH SHEN, WILLIAM STARKE, PHILLIP WILLIAMS
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Patent number: 10152385Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: July 3, 2014Date of Patent: December 11, 2018Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10133641Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: November 7, 2017Date of Patent: November 20, 2018Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10108498Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.Type: GrantFiled: February 19, 2016Date of Patent: October 23, 2018Assignee: International Business Machines CorporationInventors: Guy Lynn Guthrie, Naresh Nayar, Geraint North, Hugh Shen, William Starke, Phillip Williams
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Patent number: 10013264Abstract: In an embodiment, a request is received for a first partition to execute on a first virtual processor. If the first physical processor is available at a first node, the first virtual processor is dispatched to execute at the first physical processor at the first node that is the home node of the first virtual processor. If the first physical processor is not available, a determination is made whether the first physical processor is assigned to a second virtual processor and a home node of the second virtual processor is not the first node. If the first physical processor is assigned to a second virtual processor and the home node of the second virtual processor is not the first node, execution of the second virtual processor is stopped on the first physical processor and the first virtual processor is dispatched to the first physical processor.Type: GrantFiled: September 9, 2015Date of Patent: July 3, 2018Assignee: International Business Machines CorporationInventors: Stuart Z. Jacobs, David A. Larson, Naresh Nayar
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Publication number: 20180150365Abstract: A mechanism is provided for disaster recovery of managed systems. Responsive to an identification of a virtual machine recovery condition occurring at a first node site, one or more virtual machines to be recovered to a second site node are identified. Further responsive to the identification of the virtual machine recovery condition occurring at the first node site and responsive to the identification of the one or more virtual machines to be recovered, at least some of records/metadata state data associated with the one or more virtual machines are transmitted to the second site node.Type: ApplicationFiled: November 29, 2016Publication date: May 31, 2018Inventors: Josep Cors, Richard E. Harper, Naresh Nayar, Gerhard A. Widmayer
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Publication number: 20180121675Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Giles R. Frazier, Bruce Mealey, Naresh Nayar
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Patent number: 9948711Abstract: A method, executed by a computer, for allocating resources includes assigning resiliency attributes to a server having a workload, linking each server to a partner resource, duplicating the workload of each server in an offsite location accessible to the partner resource, detecting a disaster event, and transferring the workload of the server automatically to the partner resource. In some embodiments, the partner resource is a plurality of pool servers. The partner resource may be calculated by performing a capacity analysis. The partner resource may not a specifically assigned resource until a disaster occurs. In some embodiments, the workload is duplicated such that the recovery point objective of the workload is minimized. A computer program product and computer system corresponding to the methods are also disclosed herein.Type: GrantFiled: June 15, 2015Date of Patent: April 17, 2018Assignee: International Business Machines CorporationInventors: Josep Cors, Naresh Nayar, Birgit M. Pfitzmann, Suraj Subramanian, Gerhard A. Widmayer
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Patent number: 9935824Abstract: In an approach for provisioning a server utilizing a virtual consistency group, a processor receives a request to provision a first server utilizing a first application consistency group, wherein the first application consistency group is a virtualized consistency group. A processor defines a storage consistency group. A processor assigns the first application consistency group to the storage consistency group. A processor provisions the first server. A processor assigns to the provisioned first server, storage specified by the first application consistency group.Type: GrantFiled: June 15, 2015Date of Patent: April 3, 2018Assignee: International Business Machines CorporationInventors: Josep Cors, Naresh Nayar, Suraj Subramanian, Oliver M. Voigt, Gerhard A. Widmayer