Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Abstract: A method to generate an executable orchestration process includes: querying a user to enter first computer code for activating a service; querying the user to enter second computer code for undoing actions performed in the activating; loading pre-defined third computer code for determining whether the activated service is a success or has an error, based on the service; loading pre-defined fourth computer code for correcting the error; generating an executable orchestration function from the first through fourth computer code; and generating the orchestration process from the executable orchestration function.

Abstract: Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.

Abstract: A method, executed by a computer, for allocating resources includes assigning resiliency attributes to a server having a workload, linking each server to a partner resource, duplicating the workload of each server in an offsite location accessible to the partner resource, detecting a disaster event, and transferring the workload of the server automatically to the partner resource. In some embodiments, the partner resource is a plurality of pool servers. The partner resource may be calculated by performing a capacity analysis. The partner resource may not a specifically assigned resource until a disaster occurs. In some embodiments, the workload is duplicated such that the recovery point objective of the workload is minimized. A computer program product and computer system corresponding to the methods are also disclosed herein.

Abstract: In an approach for provisioning a server utilizing a virtual consistency group, a processor receives a request to provision a first server utilizing a first application consistency group, wherein the first application consistency group is a virtualized consistency group. A processor defines a storage consistency group. A processor assigns the first application consistency group to the storage consistency group. A processor provisions the first server. A processor assigns to the provisioned first server, storage specified by the first application consistency group.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines, a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, periodically check the image modification flags and write only the memory address of the flagged cache rows in the defined log. The processor unit is further arranged to monitor the free space available in the defined log and to trigger an interrupt if the free space available falls below a specific amount.

Abstract: Disclosed is a computer implemented method, computer program product, and apparatus to establish at least one paging partition in a data processing system. The virtualization control point (VCP) reserves up to the subset of physical memory for use in the shared memory pool. The VCP configures at least one logical partition as a shared memory partition. The VCP assigns a paging partition to the shared memory pool. The VCP determines whether a user requests a redundant assignment of the paging partition to the shared memory pool. The VCP assigns a redundant paging partition to the shared memory pool, responsive to a determination that the user requests a redundant assignment. The VCP assigns a paging device to the shared memory pool. The hypervisor may transmit at least one paging request to a virtual asynchronous services interface configured to support a paging device stream.

Abstract: Memory page de-duplication in a computer system that includes a plurality of virtual machine partitions managed by a hypervisor, where each virtual machine is assigned a different dedicated memory partition, may include: identifying, by the hypervisor, a plurality of identical memory pages in memory of one or more dedicated memory partitions; assigning, by the hypervisor, one of the identical memory pages as a master page; mapping, for each virtual machine having an identical memory page, each of the identical memory pages to the master page; and directing, by the hypervisor, reads of the memory page to the master page.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Abstract: A computer system comprises a processor unit arranged to run a hypervisor running one or more virtual machines; a cache connected to the processor unit and comprising a plurality of cache rows, each cache row comprising a memory address, a cache line and an image modification flag; and a memory connected to the cache and arranged to store an image of at least one virtual machine. The processor unit is arranged to define a log in the memory and the cache further comprises a cache controller arranged to set the image modification flag for a cache line modified by a virtual machine being backed up, but not for a cache line modified by the hypervisor operating in privilege mode; periodically check the image modification flags; and write only the memory address of the flagged cache rows in the defined log.

Abstract: Multiple machine state registers are included in a processor core to permit distinction between use of hardware facilities by applications, supervisory threads and the hypervisor. All facilities are initially disabled by the hypervisor when a partition is initialized. When any access is made to a disabled facility, the hypervisor receives an indication of which facility was accessed and sets a corresponding hardware flag in the hypervisor's machine state register. When an application attempts to access a disabled facility, the supervisor managing the operating system image receives an indication of which facility was accessed and sets a corresponding hardware flag in the supervisor's machine state register. The multiple register implementation permits the supervisor to determine whether particular hardware facilities need to have their state saved when an application context swap occurs and the hypervisor can determine which hardware facilities need to have their state saved when a partition swap occurs.

Abstract: Memory page de-duplication in a computer system that includes a plurality of virtual machine partitions managed by a hypervisor, where each virtual machine is assigned a different dedicated memory partition, may include: identifying, by the hypervisor, a plurality of identical memory pages in memory of one or more dedicated memory partitions; assigning, by the hypervisor, one of the identical memory pages as a master page; mapping, for each virtual machine having an identical memory page, each of the identical memory pages to the master page; and directing, by the hypervisor, reads of the memory page to the master page.

Abstract: Profile properties in a partition profile are user-configurable through a management entity such as a management console. A partition manager calculates a secondary processing unit entitlement for a logical partition based in part on a secondary processing unit mode property in the partition profile. The secondary processing unit entitlement may be smaller than a primary processing unit entitlement for the logical partition. The partition manager reserves processing units from a secondary shared processor pool equal to the logical partition's secondary entitlement for the logical partition. The primary and secondary processing unit entitlements may be stored in primary and secondary configuration data structures associated with the logical partition. The partition manager may relocate the logical partition to the secondary shared processor pool in response to a predetermined condition.

Abstract: Profile properties in a partition profile are user-configurable through a management entity such as a management console. A partition manager calculates a secondary processing unit entitlement for a logical partition based in part on a secondary processing unit mode property in the partition profile. The secondary processing unit entitlement may be smaller than a primary processing unit entitlement for the logical partition. The partition manager reserves processing units from a secondary shared processor pool equal to the logical partition's secondary entitlement for the logical partition. The primary and secondary processing unit entitlements may be stored in primary and secondary configuration data structures associated with the logical partition. The partition manager may relocate the logical partition to the secondary shared processor pool in response to a predetermined condition.