Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate and a trench. The silicon carbide semiconductor substrate has an offset angle with respect to a (0001) plane or a (000-1) plane and has an offset direction in a <11-20> direction. The trench is provided from a surface of the silicon carbide semiconductor substrate. The trench extends in a direction whose interior angle with respect to the offset direction is 30 degrees or ?30 degrees.

Abstract: An SiC semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate oxide film, a gate electrode, a source electrode and a drain electrode. The substrate has a Si-face as a main surface. The source region has the Si-face. The trench is provided from a surface of the source region to a portion deeper than the base region and extends longitudinally in one direction and has a Si-face bottom. The trench has an inverse tapered shape, which has a smaller width at an entrance portion than at a bottom, at least at a portion that is in contact with the base region.

Abstract: A manufacturing method of an SiC single crystal includes preparing an SiC substrate, implanting ions into a surface portion of the SiC substrate to form an ion implantation layer, activating the ions implanted into the surface portion of the SiC substrate by annealing, chemically etching the surface portion of the SiC substrate to form an etch pit that is caused by a threading screw dislocation included in the SiC substrate and performing an epitaxial growth of SiC to form an SiC growth layer on a surface of the SiC substrate including an inner wall of the etch pit in such a manner that portions of the SiC growth layer grown on the inner wall of the etch pit join with each other.

Abstract: A SiC semiconductor device includes: a substrate, a drift layer, and a base region stacked in this order; first and second source regions and a contact layer in the base region; a trench penetrating the source and base regions; a gate electrode in the trench; an interlayer insulation film with a contact hole covering the gate electrode; a source electrode coupling with the source region and the contact layer via the contact hole; a drain electrode on the substrate; and a metal silicide film. The high concentration second source region is shallower than the low concentration first source region, and has a part covered with the interlayer insulation film, which includes a low concentration first portion near a surface and a high concentration second portion deeper than the first portion. The metal silicide film on the second part has a thickness larger than the first portion.

Abstract: Provided are a vertical nitride semiconductor device in which occurrence of leak currents can be suppressed, and a method for manufacturing such nitride semiconductor device. A nitride semiconductor device, which is a vertical HEMT, is provided with an n? type GaN first nitride semiconductor layer, p+ type GaN second nitride semiconductor layers, an n? type GaN third nitride semiconductor layer, and an n? type AlGaN fourth nitride semiconductor layer that is in hetero junction with a front surface of the third nitride semiconductor layer. Openings that penetrate the third nitride semiconductor layer and reach front surfaces of the second nitride semiconductor layers are provided at positions isolated from the peripheral edge of the third nitride semiconductor layer. Source electrodes are provided in the openings. Etching damage that is in contact with the source electrodes is surrounded by a region where no etching damage is formed.

Abstract: A semiconductor device includes a semiconductor substrate and an electric field terminal part. The semiconductor substrate includes a substrate, a drift layer disposed on a surface of the substrate, and a base layer disposed on a surface of the drift layer. The semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region. The base region has a bottom face located on a same plane throughout the cell region and the peripheral region and provides an electric field relaxing layer located in the peripheral region. The electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer and penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer.

Abstract: The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench.

Abstract: A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.

Abstract: In a method of manufacturing a silicon carbide substrate, a defect-containing substrate made of silicon carbide is prepared. The defect-containing substrate has a front surface, a rear surface being opposite to the front surface, and a surface portion adjacent to the front surface. The detect-containing substrate includes a screw dislocation in the surface portion. The front surface of the defect-containing substrate is applied with an external force so that a crystallinity of the surface portion is reduced. After being applied with the external force, the defect-containing substrate is thermally treated so that the crystallinity of the surface portion is recovered.

Abstract: A method for manufacturing a semiconductor device including a semiconductor substrate composed of silicon carbide, an upper surface electrode which contacts an upper surface of the substrate, and a lower surface electrode which contacts a lower surface of the substrate, the method including steps of: (a) forming an upper surface structure on the upper surface side of the substrate, and (b) forming a lower surface structure on the lower surface side of the substrate. The step (a) comprises steps of: (a1) depositing an upper surface electrode material layer on the upper surface of the substrate, the upper surface electrode material layer being a raw material layer of the upper surface electrode, and (a2) annealing the upper surface electrode material layer.

Abstract: A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm?3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.

Abstract: A semiconductor device 10 comprises a heterojunction between a lower semiconductor layer 26 made of p-type gallium nitride and an upper semiconductor layer 28 made of n-type AlGaN, wherein the upper semiconductor layer 28 has a larger band gap than the lower semiconductor layer 26. The semiconductor device 10 further comprises a drain electrode 32 formed on a portion of a top surface of the upper semiconductor layer 28, a source electrode 34 formed on a different portion of the top surface of the upper semiconductor layer 28, and a gate electrode 36 electrically connected to the lower semiconductor layer 26. The semiconductor device 10 can operate as normally-off.

Abstract: A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm?3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.

Abstract: The present invention aims to suppress the diffusion of p-type impurities (typically magnesium), included in a semiconductor region of a III-V compound semiconductor, into an adjoining different semiconductor region. A semiconductor device 10 of the present invention comprises a first semiconductor region 28 of gallium nitride (GaN) including p-type impurities that consist of magnesium, a second semiconductor region 34 of gallium nitride, and an impurity diffusion suppression layer 32 of silicon oxide (SiO2) located between the first semiconductor region 28 and the second semiconductor region 34.

Abstract: A semiconductor device 10 comprises a heterojunction between a lower semiconductor layer 26 made of p-type gallium nitride and an upper semiconductor layer 28 made of n-type AlGaN, wherein the upper semiconductor layer 28 has a larger band gap than the lower semiconductor layer 26. The semiconductor device 10 further comprises a drain electrode 32 formed on a portion of a top surface of the upper semiconductor layer 28, a source electrode 34 formed on a different portion of the top surface of the upper semiconductor layer 28, and a gate electrode 36 electrically connected to the lower semiconductor layer 26. The semiconductor device 10 can operate as normally-off.

Abstract: A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.

Abstract: The semiconductor device has a stacked structure in which a p-GaN layer 32, an SI-GaN layer 62, and an AlGaN layer 34 are stacked, and has a gate electrode 44 that is formed at a top surface side of the AlGaN layer 34. A band gap of the AlGaN layer 34 is wider than a band gap of the p-GaN layer 32 and the SI-GaN layer 62. Moreover, impurity concentration of the SI-GaN layer 62 is less than 1×1017 cm?3. The semiconductor devices comprising III-V semiconductors that have a stable normally-off operation are realized.