Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

Abstract: The computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Creating by a computer an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Creating an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of one or more of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the one or more of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

Abstract: System and methods for achieving a timing closure in a design of an integrated circuit in presence of manufacturing variation. The method includes running a timing engine of a statistical timing analysis tool performing at least one optimization to fix at least one violation of at least one timing quantity at an integrated circuit location. The method includes choosing at least one optimization to apply and finding at least one failing timing quantity, where the quantity is failing due to at least one source of variability which the optimization would impact. The optimization is applied to at least one section of the path leading to the failing timing quantity, where the section contributes to the source of variability. Statistical sensitivity information in canonical form guides the optimization by providing a fully parameterized canonical form of the identified timing violations.

Abstract: A method, system, and computer program product to perform dynamic voltage frequency scaling of an integrated circuit include performing statistical timing analysis using a canonical form of a clock, the canonical form of the clock being a function of variability in voltage. Obtaining a canonical model expressing timing slack at each test location of the integrated circuit is as a function of one or more sources of variability, one of the one or more sources of variability being voltage, and performing the dynamic voltage-frequency scaling based on selecting at least one of a clock period and the voltage using the canonical model.

Abstract: A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.

Abstract: A method performs statistical static timing analysis of a network that includes a phase-locked loop and a feedback path. The feedback path comprises a set of delays operatively connected from the output of the phase-locked loop back to the input of the phase-locked loop. One embodiment herein computes a statistical feedback path delay for the feedback path. The method can use a separate statistical parameter to represent random uncorrelated delay variation for each delay in the feedback path. The method also computes an output arrival time for the phase-locked loop based on the negative of the statistical feedback path delay.

Abstract: In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree.

Abstract: In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree.

Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

Abstract: A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.

Abstract: An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks.

Abstract: A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.

Abstract: A method performs statistical static timing analysis of a network that includes a phase-locked loop and a feedback path. The feedback path comprises a set of delays operatively connected from the output of the phase-locked loop back to the input of the phase-locked loop. One embodiment herein computes a statistical feedback path delay for the feedback path. The method can use a separate statistical parameter to represent random uncorrelated delay variation for each delay in the feedback path. The method also computes an output arrival time for the phase-locked loop based on the negative of the statistical feedback path delay.