Abstract: An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks.

Abstract: Methods for identifying failing timing requirements in a digital design. The method includes identifying at least one timing test in the digital design that has a passing slack in a base process corner and a failing slack in a different process corner. The method further includes computing a sensitivity of the failing slack to each of a plurality of variables and comparing each sensitivity to a respective sensitivity threshold. If the sensitivity of at least one of the variables is greater than the respective sensitivity threshold, then the at least one timing test is considered to fail.

Abstract: Methods for analyzing timing of an integrated circuit using block-based static statistical timing analysis and for practical worst test definition and debug. The method includes building a timing graph, determining a slack for each of the nodes in the timing graph, and identifying a statistically worst slack for at least one of the nodes. The method further includes replacing this statistically worst slack with a proxy worst slack.

Abstract: A method of evaluating an integrated circuit design selects manufacturing parameters of interest which are outside of manufacturing specification limits. Then, the method runs timing tests on the integrated circuit design and successively evaluates the timing test results in an iterative process that considers the timing performance sensitivity to the selected manufacturing parameters of interest. The design is made more robust to each parameter out of manufacturing range.

Abstract: A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. In one example, a decreasing parameter order is utilized to order slack cutoff values that are assigned across a parameter process space. In another example, a decreasing parameter order is utilized to perform a multi-corner timing analysis on one or more dependent parameters in an independent fashion.

Abstract: A method and system for reducing a number of paths to be analyzed in a multi-corner static timing analysis. An estimated upper slack variation based on a non-common path delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path. In another example, an estimated maximum RSS credit based on a total delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path.

Abstract: A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, slack cutoff values are assigned across a parameter process space. For example, a slack cutoff value is assigned to each parameter in a process space by determining an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space. In another embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing.

Abstract: A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis.

Abstract: Methods for identifying failing timing requirements in a digital design. The method includes identifying at least one timing test in the digital design that has a passing slack in a base process corner and a failing slack in a different process corner. The method further includes computing a sensitivity of the failing slack to each of a plurality of variables and comparing each sensitivity to a respective sensitivity threshold. If the sensitivity of at least one of the variables is greater than the respective sensitivity threshold, then the at least one timing test is considered to fail.

Abstract: Methods for analyzing timing of an integrated circuit using block-based static statistical timing analysis and for practical worst test definition and debug. The method includes building a timing graph, determining a slack for each of the nodes in the timing graph, and identifying a statistically worst slack for at least one of the nodes. The method further includes replacing this statistically worst slack with a proxy worst slack.

Abstract: A method of evaluating an integrated circuit design selects manufacturing parameters of interest which are outside of manufacturing specification limits. Then, the method runs timing tests on the integrated circuit design and successively evaluates the timing test results in an iterative process that considers the timing performance sensitivity to the selected manufacturing parameters of interest. The design is made more robust to each parameter out of manufacturing range.

Abstract: A method of timing closure for integrated circuit designs uses multiple timing runs which distribute the frequency of identified fails per timing corner (between starting timing corners and remaining timing corners) to maximize efficiency in timing analysis. More specifically, the method closes timing for a chosen set of starting timing corners, verifies the remaining timing corners are orthogonal to the starting timing corners, closes timing for the remaining timing corners using multi-corner analysis, and verifies that all timing corners have positive slack margin.

Abstract: Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.

Abstract: A method and system for reducing a number of paths to be analyzed in a multi-corner static timing analysis. An estimated upper slack variation based on a non-common path delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path. In another example, an estimated maximum RSS credit based on a total delay for a racing path is utilized in determining if a multi-corner static timing analysis may be bypassed for a racing path.

Abstract: A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing. In one example, a decreasing parameter order is utilized to order slack cutoff values that are assigned across a parameter process space. In another example, a decreasing parameter order is utilized to perform a multi-corner timing analysis on one or more dependent parameters in an independent fashion.

Abstract: A method and system for decreasing processing time in multi-corner static timing analysis. In one embodiment, slack cutoff values are assigned across a parameter process space. For example, a slack cutoff value is assigned to each parameter in a process space by determining an estimated maximum slack change between a starting corner and any other corner in a corresponding process sub-space. In another embodiment, parameters are ordered in a parameter order by decreasing magnitude of impact on variability of timing.

Abstract: Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.