Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) a first signal and a second signal in response to a pump down signal and (ii) a third signal and a fourth signal in response to (i) a pump up signal. The second circuit may be configured to generate (a) a first control signal in response to (i) the first signal and (ii) the third signal and (b) a second control signal in response to (i) the second signal and (ii) the fourth signal.

Abstract: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first current in response to a first input signal. The second circuit may be configured to generate a second current in response to a second input signal. The third circuit may be configured to present a first pulse of current at a first output or a second pulse of current at a second output in response to the first and second currents.

Abstract: A circuit comprising a plurality of input devices, a plurality of de-select devices and a selector device. The plurality of input devices may each be configured to receive an input signal. The plurality of de-select devices may each be configured to present an output in response (i) one of the plurality of inputs and (ii) one of a plurality of de-select signals. The selector device may be configured to present the plurality of de-select signals. In general, all but one of the de-select signals is active at a time.

Abstract: An architecture comprising a detector, a first pump circuit, a second pump circuit and a comparator. The detector may present a first active operating signal in response to one or more reference signals. In one example, the first active operating signal may be generated in response to a feedback signal having a parameter within a predetermined range. The first pump circuit may be configured to provide a replica pump signal in response to a current adjustment signal and either (i) at least one of the one or more reference signals or (ii) the first active operating signal. The second pump circuit may be configured to provide a voltage control signal in response to the current adjustment signal and either (i) the first active operating signal or (ii) a second, independent active operating signal. The comparator may be configured to provide the current adjustment signal in response to the replica pump signal and the voltage control signal.

Abstract: A circuit and method for preventing an oscillator from oscillating above a first predetermined frequency or below a second predetermined frequency. The present invention may comprise (a) a clock generation circuit configured to generate an output clock signal in response to (i) a reference clock, (ii) one or more control signals and (ii) a reset signal and (b) a control circuit configured to generate said reset signal in response to said one or more control signals.

Abstract: A test device for testing an integrated circuit fabricated according to a process is disclosed. The device includes a layout structure, and a excitation circuit. The layout structure includes a plurality of branch structures which are arranged in parallel. Each branch structure includes a feature having a predetermined dimension. The dimension of the feature between associated with adjacent branch structures increases/decreases so as to cover an entire, predetermined spectrum or range of predetermined minimum dimensions. The feature is present (i.e., formed) in a respective branch structure when the process bias/resolution supports fabrication of that dimension. Otherwise, that feature is absent. The excitation circuit is adapted to provide a current through each branch structure to the extent the feature in the branch structure is present. All the branch currents are collected at a common node. If the feature is absent, the current will not be carried, and will thus not contribute to the total current.

Abstract: A buffer circuit or output driver can produce a common-mode output and maintain fully differential input signals to the buffer. The common-mode output is derived by shifting the input voltages to the buffer by a threshold amount, averaging the shifted input voltages through a resistor divider, then again-shifting the resulting voltage to an output node of the buffer. The voltages at which the first and second shifts occur are equal but in opposite direction. Accordingly, the output voltage is at a midscale, average or common-mode voltage of the input voltages applied to the buffer. The output voltage has sufficient swing head room and is well suited for low power applications. The buffer circuit utilizes relatively few transistors and only two major current paths from the power supply to ground. Accordingly, the buffer consumes relatively low amounts of power.

Abstract: An improved clock generation circuit is provided for changing the phase of one signal relative to the phase of another signal. Both signals presented to the clock generation circuit transition at the same frequency. One or both of those signals are delayed by dissimilar amounts to skew the phase difference between the signal pairs and 90.degree.. A phase detector, or logic gate, determines a phase differential between the incoming signals. A charge pump and storage device maintain a voltage level commensurate with that difference. The stored voltage is then used to control a feedback loop coupled from the output of the detector to a current path which traverses a buffer coupled between an input signal and a phase compensated output signal. The current path receives current necessary to change both the rise and fall rates produced by the buffer. According to another embodiment, two feedback loops may be used for a corresponding pair of buffers.

Abstract: A voltage controlled oscillator (VCO) having a current gain compensation circuit includes a control circuit portion for generating a frequency control signal, and a ring oscillator responsive to the frequency control signal for outputting the VCO output signal. The control circuit includes a control transistor responsive to input control voltage V.sub.control. Connected between the source terminal of the control transistor and ground is a resistive element in parallel with an N-channel field effect transistor and a P-channel field effect transistor, each configured to operate in saturation. The resistor, and the N-channel, and P-channel transistors provide parallel current paths which, collectively, form a control current that corresponds to the frequency control signal. As the voltage control signal V.sub.control increases beyond a predetermined level, the transistors conduct, and carry a current that is proportional to the square of the input control voltage V.sub.control.

Abstract: A voltage controlled oscillator (VCO) having a current gain compensation circuit includes a control circuit portion for generating a frequency control signal, and a ring oscillator responsive to the frequency control signal for outputting the VCO output signal. The control circuit includes a control transistor responsive to input control voltage V.sub.control. Connected between the source terminal of the control transistor and ground is a resistive element in parallel with an N-channel field effect transistor and a P-channel field effect transistor, each configured to operate in saturation. The resistor, and the N-channel, and P-channel transistors provide parallel current paths which, collectively, form a control current that corresponds to the frequency control signal. As the voltage control signal V.sub.control increases beyond a predetermined level, the transistors conduct, and carry a current that is proportional to the square of the input control voltage V.sub.control.