Abstract: The present invention discloses compositions and methods for enhancing the effect (e.g., duration) of a neurotoxin treatment. The compositions herein include neurotoxins and neuron growth inhibitors. Such compositions are administered locally to treat or prevent conditions, such as dermatological conditions, urological conditions, thyroid conditions, optical conditions, and neurological conditions.

Abstract: A system for correcting the intensities of pixels supplied to a projector. An image generated by the projector has a number of regions formed by the overlapping of the image with one or more other images generated by one or more other projectors. The system includes: a first unit configured to generate a horizontal scaling value; a second unit configured to generate a vertical scaling value; a first multiplier configured to multiply the horizontal scaling value and the vertical scaling value to obtain a scaling coefficient, and a set of one or more additional multipliers configured to multiply components of an input pixel by the scaling coefficient to determine components for an output pixel. The first unit and second unit compute their respective scaling values in a way that allows for regions whose boundaries non-aligned in the vertical direction.

Abstract: Compositions and method for augmenting tissue after delivery to localized area. The compositions include a hydrogel and a dermal filler. The hydrogel can polymerize and/or crosslink upon a first trigger event. The dermal filler can also optionally crosslink upon a second trigger event.

Abstract: A multi-chip system is disclosed for distributing the convolution process. Rather than having multiple convolution chips working in parallel with each chip working on a different portion of the screen, a new design utilizes chips working in series. Each chip is responsible for a different interleaved region of screen space. Each chip performs part of the convolution process for a pixel and sends a partial result on to the next chip. The final chip completes the convolution and stores the filtered pixel. An alternate design interconnects chips in groups. The chips within a group operate in series, whereas the groups may operate in parallel.

Abstract: A computer system may include several integrated circuits and a routing circuit configured to route several data streams between the integrated circuits. The routing circuit includes several input ports, several output ports, and a signature analysis register coupled to one of the output ports. The signature analysis register is configured to collect data conveyed via the output port dependent upon whether the signature analysis register receives a tag identifying one of the plurality of data streams.

Abstract: A graphics system comprising a set of rendering processors and a series of filtering units. Each of the rendering processors couples to a corresponding one of the filtering units. Each rendering processor RP(K) is configured to (a) generate a stream of samples in response to received graphics primitives, (b) add a dither value DK to a data component of each the samples in the stream to obtain dithered data components, (c) buffer the dithered data components in an internal frame buffer, and (d) forward a truncated version of the dithered data components to the corresponding filtering unit. The filtering units are configured to perform a weighted averaging computation on the truncated dithered data components in a pipelined fashion to determine pixel data components.

Abstract: In order to synchronize two dissimilar video formats, two or more phase locked loop circuits (PLL's) may be used in tandem. A first PLL circuit may be connected to the first video format (Master) and generate an intermediate frequency. A second PLL circuit may use the intermediate frequency as the timebase for generating the pixel clock for the second video format (Slave). One or more Slaves may be connected to the generated pixel clock. The video synchronizing device may be a part of a graphics system, such as a graphics accelerator.

Abstract: The present invention provides methods and compositions for said inhibition of drug resistance. In one embodiment, said invention provides methods and compositions for said inhibition of antibiotic resistance. The invention generally involves said administration of achaogens, agents that inhibit said mutational process, to inhibit said evolution of drug resistance. Also, described herein are compositions that are suitable for use as achaogens.

Abstract: A video routing system including a plurality of video routers VR(0), VR(1), . . . , VR(NR?1) coupled in a linear series. Each video router in the linear series may successively operate on a digital video stream. Each video router provides a synchronous clock along with its output video stream so a link interface buffer in the next video router can capture values from the output video stream in response to the synchronous clock. A common clock signal is distributed to each of the video routers. Each video router buffers the common clock signal to generate an output clock. The output clock is used as a read clock to read data out of the corresponding link interface buffer. The output clock is also used to generate the synchronous clock that is transmitted downstream.

Abstract: A graphic system may include a pixel synthesizing device that uses two or more phase-locked loops (PLL's) in tandem in order to achieve a better M/N ratio. The two PLL's connected in tandem have an effective M/N ratio of (M1*M2)/(N1*N2). The pixel synthesizing device is operable to synthesize free-running (non-genlocked, or sync-master) pixel clock frequencies using a much greater variety of M and N. As a result, greater precision in specification of the pixel clock frequency is achieved, yielding greater precision in a frame rate of a particular video format. As a result, the allowable channel spacing is greatly increased, and the graphic system can select from a wide range of ultradense spaced pixel clocks.

Abstract: One embodiment of a method of frame detection may involve storing data indicative of a pulse duration and a number of successive occurrences of pulses having that pulse duration for each of several different pulse durations detected within a first field of a composite synchronization signal. This process may be repeated for one or more other fields of the composite synchronization signal. The data stored for each of the fields may be compared, and a frame signal may be generated dependent on an outcome of said comparing.

Abstract: A graphics system configured with a scheduling network, a sample buffer, a rendering engine and a filtering engine. The rendering engine is configured to generate samples in response to received graphics data, and to forward the samples to the scheduling network for storage in the sample buffer. The filtering engine is configured to send a request for samples to the scheduling network. The scheduling network is configured to compare a video set designation of the request to a previous request designation, to update one or more state registers in one or more memory devices of the sample buffer in response to a determination that the video set designation of the request is different from the previous request designation, and to assert signals inducing a transfer of a collection of samples corresponding to the request from the one or more memory devices to the filtering engine.

Abstract: A graphics system comprising a plurality of rendering pipelines and a scheduling network. Each rendering pipeline couples to the scheduling network, and includes a media processor, a rendering unit and a memory. A communication bus may couple the scheduling network and the memory of each rendering pipeline. The media processor in each rendering pipeline may direct the saving of state information of the corresponding rendering pipeline to the corresponding memory in response to receiving a corresponding context switch indication. A first of the media processors initiates the transfer of a resume token to the scheduling network through the corresponding rendering pipeline if the context switch occurs during an ordered processing mode. The scheduling network unblocks one or more rendering pipelines other than the first rendering pipeline in response to receiving the resume token.

Abstract: The present invention discloses compositions and methods for enhancing the effect (e.g., duration) of a neurotoxin treatment. The compositions herein include neurotoxins and neuron growth inhibitors. Such compositions are administered locally to treat or prevent conditions, such as dermatological conditions, urological conditions, thyroid conditions, optical conditions, and neurological conditions.

Abstract: Novel compositions and methods and pharmaceutical compositions for altering skin coloration. The methods include administering a cytokine to a dermal region desired to be altered. The cytokine is formulated for local administration. The cytokine is preferably administered in conjunction with a therapeutic procedure. The therapeutic procedure is preferably selected from the group consisting of excision, dermabrasion, laser therapy, cryosurgery, grafting, camouflaging, scarification, and salabrasion.

Abstract: The present invention discloses compositions and methods for the prevention and treatment of skin and hair diseases, such as, for example, alopecia, psoriasis, and keloids. In one embodiment, the present invention discloses a method for preventing and treating hair loss by applying locally to a region lacking hair a p38? MAP kinase inhibitor. The p38? MAP kinase inhibitor is preferably formulated as a gel, ointment, spray or solution that can be applied topically, transdermally, or subcutaneously to the targeted region.

Abstract: A system and method are disclosed to allow the tiling of sample jitter patterns to be independent of the tiling of clustered graphics accelerators. Each accelerator uses an x,y “bias” offset to shift the origin of the jitter pattern within the sample space region addressed by the accelerator. In this way, multiple accelerators may be programmed so that their jitter patterns integrate into one global pattern without discontinuities at the region boundaries.

Abstract: Business methods for commercialization of antibiotics are disclosed. According to one embodiment of the invention, drugs that are found to be otherwise effective and safe, but which are not acceptable due to rapid development of resistance, are rescued by way of the use of achaogens. A biopharmaceutical company may then, for example, charge royalties or purchase such drugs for its own account.

Abstract: A system and method are disclosed for reproducing a pre-selected larger 2-D sample location pattern from a smaller one by means of X,Y address permutation. This method, for example, allows hardware to effectively reproduce a pre-selected set of sample locations for an array of 128×128 sample bins from a smaller set of pre-selected sample locations for an array of 2×2 sample bins. A permutation logic unit may use a first portion of an address for a sample bin B to identify a corresponding 2-D transformation, apply the inverse of the transformation to a second portion of the sample bin address to identify the corresponding bin of the 2×2 array of sample bins, and apply the transformation to the sample locations stored in the corresponding bin to reproduce the sample locations pre-selected for sample bin B.

Abstract: A video routing system including video routers VR(0), VR(1), . . . , VR(NR−1) coupled in a linear series. Each video router in the linear series successively operates on a digital video stream. Each video router provides a synchronous clock with its output video stream so a link interface buffer in the next video router can capture values from the output video stream in response to the synchronous clock. Each video router buffers a common clock to generate a local output clock. The output clock is used as a read clock to read data out of the corresponding link interface buffer. The output clock is also used to generate the synchronous clock that is transmitted downstream. To initialize the series, reset is sequentially removed from each video router starting from the first video router after the common clock has stabilized.