Patents by Inventor Natsuki Fukuda

Natsuki Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9704922
    Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Oga, Mutsumi Okajima, Takeshi Yamaguchi, Hiroyuki Ode, Toshiharu Tanaka, Natsuki Fukuda
  • Publication number: 20170012197
    Abstract: To provide a low-cost variable-resistance element and a production method therefor. According to an embodiment of the present invention, there is provided a variable-resistance element 1 including a lower electrode layer 3, an upper electrode layer 5, and an oxide semiconductor layer 4. The upper electrode layer 5 is formed of a carbon material. The oxide semiconductor layer 4 includes a first metal oxide layer 41 and a second metal oxide layer 42. The first metal oxide layer 41 is formed between the lower electrode layer 3 and the upper electrode layer 5 and includes a first resistivity. The second metal oxide layer 42 is formed between the first metal oxide layer 41 and the upper electrode layer 5 and includes a second resistivity different from the first resistivity.
    Type: Application
    Filed: February 13, 2015
    Publication date: January 12, 2017
    Inventors: Natsuki Fukuda, Kazunori Fukuju, Yuusuke Miyaguchi, Yutaka Nishioka, Koukou Suu
  • Publication number: 20160351628
    Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.
    Type: Application
    Filed: December 15, 2015
    Publication date: December 1, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mutsumi OKAJIMA, Atsushi OGA, Takeshi YAMAGUCHI, Hiroyuki ODE, Toshiharu TANAKA, Natsuki FUKUDA
  • Publication number: 20160351624
    Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.
    Type: Application
    Filed: September 10, 2015
    Publication date: December 1, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi OGA, Mutsumi OKAJIMA, Takeshi YAMAGUCHI, Hiroyuki ODE, Toshiharu TANAKA, Natsuki FUKUDA
  • Patent number: 9343207
    Abstract: To provide a resistance change device that can be protected from an excess current without enlarging a device size. A resistance change device 1 according to the present embodiment includes a lower electrode layer 3, an upper electrode layer 6, a first metal oxide layer 51, a second metal oxide layer 52, and a current limiting layer 4. The first metal oxide layer 51 is disposed between the lower electrode layer 3 and the upper electrode layer 6, and has a first resistivity. The second metal oxide layer 52 is disposed between the first metal oxide layer 51 and the upper electrode layer 6, and has a second resistivity higher than the first resistivity. The current limiting layer 4 is disposed between the lower electrode layer 3 and the first metal oxide layer 51, and has a third resistivity higher than the first resistivity and lower than the second resistivity.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: May 17, 2016
    Assignee: Ulvac, Inc.
    Inventors: Natsuki Fukuda, Kazunori Fukuju, Yutaka Nishioka, Koukou Suu
  • Patent number: 9281477
    Abstract: To provide a resistance change element which does not require a forming process and enables reduction of power consumption and miniaturization of the element, and to provide a method for producing it. A resistance change element 1 according to an embodiment of the present invention includes a bottom electrode layer 3, a top electrode layer 5 and an oxide semiconductor layer 4. The oxide semiconductor layer 4 has a first metal oxide layer 41 and a second metal oxide layer 42. The first metal oxide layer 41 is formed between the bottom electrode layer 3 and the top electrode layer 5, and in ohmic contact with the bottom electrode layer 3. The second metal oxide layer 42 is formed between the first metal oxide layer 41 and the top electrode layer 5, and in ohmic contact with the top electrode layer 5.
    Type: Grant
    Filed: June 17, 2012
    Date of Patent: March 8, 2016
    Assignee: ULVAC, INC.
    Inventors: Yutaka Nishioka, Kazumasa Horita, Natsuki Fukuda, Shin Kikuchi, Koukou Suu
  • Patent number: 9269903
    Abstract: [Object] To provide a method and an apparatus for manufacturing a variable resistance element by which a metal oxide layer having a desired resistivity can be precisely formed. [Solving Means] The method of manufacturing the variable resistance element according to an embodiment of the present invention includes a step of forming a first metal oxide having a first resistivity and a step of forming a second metal oxide having a second resistivity different from the first resistivity. The first metal oxide is formed on a substrate by sputtering, while sputtering a first target made of an oxide of metal, a second target made of the metal with a first power. The second metal oxide layer is formed on the first metal oxide layer by sputtering the second target with a second power different from the first power while sputtering the first target.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: February 23, 2016
    Assignee: ULVAC, INC.
    Inventors: Yutaka Nishioka, Kazumasa Horita, Natsuki Fukuda, Shin Kikuchi, Youhei Ogawa, Koukou Suu
  • Publication number: 20150056373
    Abstract: [Object] To provide a deposition method and a deposition apparatus capable of forming a metal compound layer having desired film characteristics uniformly in a substrate surface. [Solving Means] A deposition method according to an embodiment of the present invention includes evacuating an inside of a vacuum chamber 10 having a deposition chamber 101 formed inside a cylindrical partition wall 20 and an exhaust chamber 102 formed outside the partition wall 20, via an exhaust line 50 connected to the exhaust chamber 102. A process gas containing a reactive gas is introduced into the exhaust chamber 102. With the deposition chamber 101 being maintained at a lower pressure than the exhaust chamber 102, the process gas is supplied to the deposition chamber 101 via a gas flow passage 80 between the partition wall 20 and the vacuum chamber 10.
    Type: Application
    Filed: July 25, 2013
    Publication date: February 26, 2015
    Applicant: ULVAC, INC.
    Inventors: Natsuki Fukuda, Kazunori Fukuju, Yutaka Nishioka, Koukou Suu
  • Publication number: 20140361864
    Abstract: To provide a resistance change device that can be protected from an excess current without enlarging a device size. A resistance change device 1 according to the present embodiment includes a lower electrode layer 3, an upper electrode layer 6, a first metal oxide layer 51, a second metal oxide layer 52, and a current limiting layer 4. The first metal oxide layer 51 is disposed between the lower electrode layer 3 and the upper electrode layer 6, and has a first resistivity. The second metal oxide layer 52 is disposed between the first metal oxide layer 51 and the upper electrode layer 6, and has a second resistivity higher than the first resistivity. The current limiting layer 4 is disposed between the lower electrode layer 3 and the first metal oxide layer 51, and has a third resistivity higher than the first resistivity and lower than the second resistivity.
    Type: Application
    Filed: August 27, 2013
    Publication date: December 11, 2014
    Inventors: Natsuki Fukuda, Kazunori Fukuju, Yutaka Nishioka, Koukou Suu
  • Publication number: 20140166966
    Abstract: To provide a resistance change element which does not require a forming process and enables reduction of power consumption and miniaturization of the element, and to provide a method for producing it. A resistance change element 1 according to an embodiment of the present invention includes a bottom electrode layer 3, a top electrode layer 5 and an oxide semiconductor layer 4. The oxide semiconductor layer 4 has a first metal oxide layer 41 and a second metal oxide layer 42. The first metal oxide layer 41 is formed between the bottom electrode layer 3 and the top electrode layer 5, and in ohmic contact with the bottom electrode layer 3. The second metal oxide layer 42 is formed between the first metal oxide layer 41 and the top electrode layer 5, and in ohmic contact with the top electrode layer 5.
    Type: Application
    Filed: June 7, 2012
    Publication date: June 19, 2014
    Applicant: ULVAC, INC.
    Inventors: Yutaka Nishioka, Kazumasa Horita, Natsuki Fukuda, Shin Kikuchi, Koukou Suu
  • Publication number: 20140102879
    Abstract: [Object] To provide a method and an apparatus for manufacturing a variable resistance element by which a metal oxide layer having a desired resistivity can be precisely formed. [Solving Means] The method of manufacturing the variable resistance element according to an embodiment of the present invention includes a step of forming a first metal oxide having a first resistivity and a step of forming a second metal oxide having a second resistivity different from the first resistivity. The first metal oxide is formed on a substrate by sputtering, while sputtering a first target made of an oxide of metal, a second target made of the metal with a first power. The second metal oxide layer is formed on the first metal oxide layer by sputtering the second target with a second power different from the first power while sputtering the first target.
    Type: Application
    Filed: June 7, 2012
    Publication date: April 17, 2014
    Applicant: ULVAC, INC.
    Inventors: Yutaka Nishioka, Kazumasa Horita, Natsuki Fukuda, Shin Kikuchi, Youhei Ogawa, Koukou Suu