Patents by Inventor Navab Singh
Navab Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10882737Abstract: A through silicon interposer wafer and method of manufacturing the same. A through silicon interposer wafer having at least one cavity formed therein for MEMS applications and a method of manufacturing the same are provided. The through silicon interposer wafer includes one or more filled silicon vias formed sufficiently proximate to the at least one cavity to provide support for walls of the at least one cavity during subsequent processing of the interposer wafer.Type: GrantFiled: March 23, 2017Date of Patent: January 5, 2021Assignee: Agency for Science, Technology and ResearchInventors: Navab Singh, Daw Don Cheam
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Patent number: 10669152Abstract: Various embodiments may provide a device arrangement. The device arrangement may include a substrate including a conductive layer. The device arrangement may further include a microelectromechanical systems (MEMS) device monolithically integrated with the substrate, wherein the MEMS device may be electrically coupled to the conductive layer. A cavity may be defined through the conductive layer for acoustically isolating the MEMS device MEMS device from the substrate. At least one anchor structure may be defined by the conductive layer to support the MEMS device.Type: GrantFiled: October 6, 2016Date of Patent: June 2, 2020Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Navab Singh, Jae Wung Lee, Srinivas Merugu
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Publication number: 20200145762Abstract: Various embodiments may provide an acoustic device. The acoustic device may include a substrate, an electrically conductive first membrane, a first spacer holding the first membrane to form a first acoustic chamber between the substrate and the first membrane. The acoustic device may additionally include an electrically conductive second membrane, a second spacer holding the second membrane to form a second acoustic chamber between the first membrane and the second membrane, and a plurality of electrical pads in electrical connection with the first membrane and the second membrane.Type: ApplicationFiled: June 19, 2018Publication date: May 7, 2020Inventors: Navab Singh, Xiaolin Zhang, Wing Wai Chung
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Publication number: 20190084826Abstract: A Through Silicon Interposer Wafer and Method of Manufacturing the Same A through silicon interposer wafer having at least one cavity formed therein for MEMS applications and a method of manufacturing the same are provided. The through silicon interposer wafer includes one or more filled silicon vias formed sufficiently proximate to the at least one cavity to provide support for walls of the at least one cavity during subsequent processing of the interposer wafer.Type: ApplicationFiled: March 23, 2017Publication date: March 21, 2019Inventors: Navab SINGH, Daw Don CHEAM
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Publication number: 20180312399Abstract: Various embodiments may provide a device arrangement. The device arrangement may include a substrate including a conductive layer. The device arrangement may further include a microelectromechanical systems (MEMS) device monolithically integrated with the substrate, wherein the MEMS device may be electrically coupled to the conductive layer. A cavity may be defined through the conductive layer for acoustically isolating the MEMS device MEMS device from the substrate. At least one anchor structure may be defined by the conductive layer to support the MEMS device.Type: ApplicationFiled: October 6, 2016Publication date: November 1, 2018Inventors: Navab SINGH, Jae Wung LEE, Srinivas MERUGU
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Patent number: 9650237Abstract: An electromechanical device and method of fabrication thereof comprising: providing a first wafer with a circuit arrangement on a first surface thereof and a first electrode on a second surface thereof; forming first and second via structures from the first surface to the second surface of the first wafer, said first via electrically connecting the first electrode with the circuit arrangement; providing a second wafer with a suspended structure on a first surface thereof; forming a second electrode on the suspended structure; forming an interconnect structure on the first surface of the second wafer that electrically connects with the second electrode; bonding the first wafer to the second wafer with the second surface of the first wafer facing the first surface of the second wafer, with the second via structure electrically connecting the circuit arrangement to the interconnect structure, and the first and second electrodes forming a capacitive structure.Type: GrantFiled: April 17, 2014Date of Patent: May 16, 2017Assignee: Agency for Science, Technology and ResearchInventors: Ilker E. Ocak, Julius Ming Lin Tsai, Navab Singh
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Patent number: 9505612Abstract: A method for thin film encapsulation (TFE) of a microelectromechanical system (MEMS) device, including providing a substrate; forming a MEMS device on the substrate; forming one or more etching channels adjacent to the MEMS device; providing one or more cavities below the MEMS device; and forming one or more cavities above the MEMS device.Type: GrantFiled: December 19, 2014Date of Patent: November 29, 2016Assignee: Agency for Science, Technology and ResearchInventors: Jae-Wung Lee, Jaibir Sharma, Navab Singh
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Publication number: 20160308013Abstract: A semiconductor device production method includes preparing a first structure having a first planar semiconductor layer, and a first columnar semiconductor layer on the first planar semiconductor layer. A first high concentration semiconductor layer is formed in a lower region of the first columnar semiconductor layer and in a region of the first planar semiconductor layer below the first columnar semiconductor layer. An insulating layer, a metal film, and a semiconductor film are sequentially formed on the first structure, and the semiconductor film, the metal film, and the insulating layer are sequentially etched with each leaving a sidewall shape on the sidewall on the first columnar semiconductor layer following etching. Another semiconductor film is then formed on the sidewall shape after etching the insulating film.Type: ApplicationFiled: June 24, 2016Publication date: October 20, 2016Inventors: Fujio MASUOKA, Hiroki NAKAMURA, Shintaro ARAI, Tomohiko KUDO, King-Jien CHUI, Yisuo LI, Yu JIANG, Xiang LI, Zhixian CHEN, Nansheng SHEN, Vladimir BLIZNETSOV, Kavitha Devi BUDDHARAJU, Navab SINGH
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Publication number: 20160289063Abstract: An electromechanical device and method of fabrication thereof comprising: providing a first wafer with a circuit arrangement on a first surface thereof and a first electrode on a second surface thereof; forming first and second via structures from the first surface to the second surface of the first wafer, said first via electrically connecting the first electrode with the circuit arrangement; providing a second wafer with a suspended structure on a first surface thereof; forming a second electrode on the suspended structure; forming an interconnect structure on the first surface of the second wafer that electrically connects with the second electrode; bonding the first wafer to the second wafer with the second surface of the first wafer facing the first surface of the second wafer, with the second via structure electrically connecting the circuit arrangement to the interconnect structure, and the first and second electrodes forming a capacitive structure.Type: ApplicationFiled: April 17, 2014Publication date: October 6, 2016Inventors: Ilker E. Ocak, Julius Ming Lin Tsai, Navab Singh
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Publication number: 20160289064Abstract: A method of fabricating encapsulated microelectromechanical system (MEMS) devices, comprising: providing a substrate having one or more MEMS devices formed thereon; depositing a sacrificial layer over the substrate and the one or more MEMS devices; patterning the sacrificial layer to define one or more cavities in the sacrificial layer and around the one or more MEMS devices; forming a cap layer over the sacrificial layer and the one or more cavities, the cap layer having one or more etch holes defined therein; removing the sacrificial layer by etching the sacrificial layer at least through the one or more etch holes; and depositing a sealing layer over the cap layer and the one or more etch holes to encapsulate the one or more MEMS devices, the substrate, and the cap layer.Type: ApplicationFiled: December 16, 2014Publication date: October 6, 2016Inventors: Jae-Wung Lee, Jaibir Sharma, Navab Singh
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Publication number: 20150357428Abstract: The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.Type: ApplicationFiled: August 20, 2015Publication date: December 10, 2015Inventors: Fujio MASUOKA, Hiroki NAKAMURA, Shintaro ARAI, Tomohiko KUDO, King-Jien CHUI, Yisuo LI, Yu JIANG, Xiang LI, Zhixian CHEN, Nansheng SHEN, Vladimir BLIZNETSOV, Kavitha Devi BUDDHARAJU, Navab SINGH
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Patent number: 9165932Abstract: A memory cell and a method of manufacturing a memory cell are provided. The memory cell includes a substrate; at least one first electrode disposed above the substrate; at least one second electrode disposed above the at least one first electrode; a moveable electrode disposed between the at least one first electrode and the at least one second electrode; wherein the moveable electrode is configured to move between the at least one first electrode and the at least one second electrode; wherein the moveable electrode comprises metal.Type: GrantFiled: June 25, 2012Date of Patent: October 20, 2015Assignee: Agency for Science, Technology and ResearchInventors: Vincent Pott, Navab Singh
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Patent number: 9153697Abstract: The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.Type: GrantFiled: May 26, 2011Date of Patent: October 6, 2015Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE LTD.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, King-Jien Chui, Yisuo Li, Yu Jiang, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 9087975Abstract: According to embodiments of the present invention, a resistive memory arrangement is provided. The resistive memory arrangement includes a nanowire, and a resistive memory cell including a resistive layer including a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire, and a conductive layer arranged on at least a part of the resistive layer. According to further embodiments of the present invention, a method of forming a resistive memory arrangement is also provided.Type: GrantFiled: January 21, 2013Date of Patent: July 21, 2015Assignee: Agency for Science, Technology and ResearchInventors: Xinpeng Wang, Xiang Li, Navab Singh, Guo-Qiang Patrick Lo
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Patent number: 9082838Abstract: In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.Type: GrantFiled: September 25, 2013Date of Patent: July 14, 2015Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Navab Singh, Zhixian Chen, Aashit Ramachandra Kamath, Xinpeng Wang
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Publication number: 20150175408Abstract: A method for thin film encapsulation (TFE) of a microelectromechanical system (MEMS) device, including providing a substrate; forming a MEMS device on the substrate; forming one or more etching channels adjacent to the MEMS device; providing one or more cavities below the MEMS device; and forming one or more cavities above the MEMS device.Type: ApplicationFiled: December 19, 2014Publication date: June 25, 2015Inventors: Jae-Wung Lee, Jaibir Sharma, Navab Singh
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Patent number: 8836051Abstract: A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes.Type: GrantFiled: June 3, 2013Date of Patent: September 16, 2014Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Xiang Li, Xinpeng Wang, Zhixian Chen, Aashit Ramachandra Kamath, Navab Singh
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Publication number: 20140147955Abstract: A method for encapsulating a micro-electromechanical (MEMS) device, the method comprising: providing a sacrificial layer arrangement over the MEMS device; providing a first encapsulation layer over the sacrificial layer arrangement, the first encapsulation layer defining at least one aperture; providing a second encapsulation layer over the at least one aperture, the second encapsulation layer being provided to allow removal of the sacrificial layer arrangement around the second encapsulation layer; and removing the sacrificial layer arrangement through the at least one aperture to allow the second encapsulation layer to cover the at least one aperture thereby encapsulating the MEMS device.Type: ApplicationFiled: November 29, 2013Publication date: May 29, 2014Applicant: Agency for Science, Technology and ResearchInventors: Jae-Wung Lee, Jaibir Sharma, Navab Singh, Julius Ming Ling Tsai
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Patent number: 8735750Abstract: Embodiments provide a switching device. The switching device includes a substrate, which includes a contact region. The switching device further includes a vertical layer arrangement extending from the substrate next to the contact region. The vertical layer arrangement includes a control layer. The switching device further includes a freestanding silicon cantilever extending vertically from the contact region.Type: GrantFiled: November 3, 2011Date of Patent: May 27, 2014Assignee: Agency for Science, Technology and ResearchInventors: Jiaqiang Eldwin Ng, Ming Lin Julius Tsai, Navab Singh, Nansheng Shen
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Publication number: 20140091372Abstract: In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line.Type: ApplicationFiled: September 25, 2013Publication date: April 3, 2014Applicant: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: FUJIO MASUOKA, NOZOMU HARADA, HIROKI NAKAMURA, NAVAB SINGH, ZHIXIAN CHEN, AASHIT RAMACHANDRA KAMATH, XINPENG WANG