Patents by Inventor Navab Singh
Navab Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8609494Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: GrantFiled: May 16, 2013Date of Patent: December 17, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20130328138Abstract: A method for producing a semiconductor device includes a first step including forming a planar silicon layer and forming first and second pillar-shaped silicon layers; a second step including forming a gate insulating film around each of the first and second pillar-shaped silicon layers, forming a metal film and a polysilicon film around the gate insulating film, the thickness of the polysilicon film being smaller than half of a distance between the first and second pillar-shaped silicon layers, forming a third resist, and forming a gate line; and a third step including depositing a fourth resist so that a portion of the polysilicon film on an upper side wall of each of the first and second pillar-shaped silicon layers is exposed, removing the exposed portion of the polysilicon film, removing the fourth resist, and removing the metal film to form first and second gate electrodes.Type: ApplicationFiled: June 3, 2013Publication date: December 12, 2013Inventors: FUJIO MASUOKA, NOZOMU HARADA, HIROKI NAKAMURA, XIANG LI, XINPENG WANG, ZHIXIAN CHEN, AASHIT RAMACHANDRA KAMATH, NAVAB SINGH
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Patent number: 8563379Abstract: A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.Type: GrantFiled: December 10, 2012Date of Patent: October 22, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Shintaro Arai, Hiroki Nakamura, Tomohiko Kudo, R. Ramana Murthy, Nansheng Shen, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20130270508Abstract: According to embodiments of the present invention, a non-volatile memory device is provided. The non-volatile memory device includes a nanowire transistor including a nanowire channel, and a resistive memory cell arranged adjacent to the nanowire transistor and in alignment with a longitudinal axis of the nanowire channel. According to further embodiments of the present invention, a method of forming a non-volatile memory device is also provided.Type: ApplicationFiled: April 11, 2013Publication date: October 17, 2013Applicant: Agency for Science, Technology and ResearchInventors: Xiang LI, Navab Singh, Zhixian Chen, Xinpeng Wang, Guo-Qiang Patrick Lo
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Publication number: 20130252413Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: ApplicationFiled: May 16, 2013Publication date: September 26, 2013Applicant: Unisantis Eletronics Singapore Pte.Ltd.Inventors: Fujio MASUOKA, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 8519475Abstract: A semiconductor device includes a first insulating film formed between a gate electrode and a first flat semiconductor layer, and a sidewall-shaped second insulating film formed to surround an upper sidewall of a first columnar silicon layer while contacting an upper surface of the gate electrode and to surround a sidewall of the gate electrode and the first insulating film. The semiconductor device further includes a metal-semiconductor compound formed on each of an upper surface of a first semiconductor layer of the second conductive type formed in the entirety or the upper portion of the first flat semiconductor layer, and an upper surface of the second semiconductor layer of the second conductive type formed in the upper portion of the first columnar semiconductor layer.Type: GrantFiled: November 4, 2011Date of Patent: August 27, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Navab Singh, Kavitha Devi Buddharaju, Shen Nansheng, Rukmani Devi Sayanthan
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Patent number: 8486785Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: GrantFiled: May 23, 2011Date of Patent: July 16, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 8466512Abstract: A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.Type: GrantFiled: August 18, 2010Date of Patent: June 18, 2013Assignee: Unisantis Electronics Singapore Pte Ltd.Inventors: Fujio Masuoka, Shintaro Arai, Hiroki Nakamura, Tomohiko Kudo, R. Ramana Murthy, Nansheng Shen, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20130020631Abstract: A memory cell and a method of manufacturing a memory cell are provided. The memory cell includes a substrate; at least one first electrode disposed above the substrate; at least one second electrode disposed above the at least one first electrode; a moveable electrode disposed between the at least one first electrode and the at least one second electrode; wherein the moveable electrode is configured to move between the at least one first electrode and the at least one second electrode; wherein the moveable electrode comprises metal.Type: ApplicationFiled: June 25, 2012Publication date: January 24, 2013Inventors: Vincent Pott, Navab Singh
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Patent number: 8236595Abstract: A method of fabricating a sensor comprising a nanowire on a support substrate with a first semiconductor layer arranged on the support substrate is disclosed. The method comprises forming a fin structure from the first semiconductor layer, the fin structure comprising at least two supporting portions and a fin portion arranged there between; oxidizing at least the fin portion of the fin structure thereby forming the nanowire being surrounded by a first layer of oxide; and forming an insulating layer above the supporting portions; wherein the supporting portions and the first insulating layer form a microfluidic channel. A nanowire sensor is also disclosed.Type: GrantFiled: August 11, 2006Date of Patent: August 7, 2012Assignee: Agency for Science, Technology and ResearchInventors: Ajay Agarwal, Navab Singh, Rakesh Kumar, Ieng Kin Lao, Narayanan Balasubramanian
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Publication number: 20120138437Abstract: Embodiments provide a switching device. The switching device includes a substrate, which includes a contact region. The switching device further includes a vertical layer arrangement extending from the substrate next to the contact region. The vertical layer arrangement includes a control layer. The switching device further includes a freestanding silicon cantilever extending vertically from the contact region.Type: ApplicationFiled: November 3, 2011Publication date: June 7, 2012Inventors: Jiaqiang Eldwin Ng, Ming Lin Julius Tsai, Navab Singh, Nansheng Shen
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Publication number: 20120049252Abstract: A semiconductor device includes a first insulating film formed between a gate electrode and a first flat semiconductor layer, and a sidewall-shaped second insulating film formed to surround an upper sidewall of a first columnar silicon layer while contacting an upper surface of the gate electrode and to surround a sidewall of the gate electrode and the first insulating film. The semiconductor device further includes a metal-semiconductor compound formed on each of an upper surface of a first semiconductor layer of the second conductive type formed in the entirety or the upper portion of the first flat semiconductor layer, and an upper surface of the second semiconductor layer of the second conductive type formed in the upper portion of the first columnar semiconductor layer.Type: ApplicationFiled: November 4, 2011Publication date: March 1, 2012Applicant: Unisantis Electronics Singapore PTE Ltd.Inventors: Fujio MASUOKA, Hiroki NAKAMURA, Shintaro ARAI, Tomohiko KUDO, Navab Singh, Kavitha Devi Buddharaju, Shen Nansheng, Rukmani Devi Sayanthan
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Patent number: 8080458Abstract: A method of manufacturing a semiconductor device includes the steps of forming a first columnar semiconductor layer on a substrate forming a first flat semiconductor layer forming a first semiconductor layer of a second conductive type, and forming a first insulating film. The method further includes the steps of forming a gate insulating film and a gate electrode, forming a second semiconductor layer of the second conductive type, forming a semiconductor layer of a first conductive type and forming a metal-semiconductor compound. The first insulating film has a thickness larger than that of the gate insulating film formed around the first columnar silicon layer.Type: GrantFiled: April 16, 2010Date of Patent: December 20, 2011Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Navab Singh, Kavitha Devi Buddharaju, Shen Nansheng, Rukmani Devi Sayanthan
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Publication number: 20110303985Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: ApplicationFiled: May 23, 2011Publication date: December 15, 2011Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20110303973Abstract: The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.Type: ApplicationFiled: May 26, 2011Publication date: December 15, 2011Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, King-Jien Chui, Yisuo Li, Yu Jiang, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20110193183Abstract: A method of fabricating a sensor comprising a nanowire on a support substrate with a first semiconductor layer arranged on the support substrate is disclosed. The method comprises forming a fin structure from the first semiconductor layer, the fin structure comprising at least two supporting portions and a fin portion arranged there between; oxidizing at least the fin portion of the fin structure thereby forming the nanowire being surrounded by a first layer of oxide; and forming an insulating layer above the supporting portions; wherein the supporting portions and the first insulating layer form a microfluidic channel. A nanowire sensor is also disclosed.Type: ApplicationFiled: August 11, 2006Publication date: August 11, 2011Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Ajay Agarwal, Navab Singh, Rakesh Kumar, Ieng Kin Lao, Narayanan Balasubramanian
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Publication number: 20110042740Abstract: A method for producing a semiconductor device includes preparing a structure having a substrate, a planar semiconductor layer and a columnar semiconductor layer, forming a second drain/source region in the upper part of the columnar semiconductor layer, forming a contact stopper film and a contact interlayer film, and forming a contact layer on the second drain/source region. The step for forming the contact layer includes forming a pattern and etching the contact interlayer film to the contact stopper film using the pattern to form a contact hole for the contact layer and removing the contact stopper film remaining at the bottom of the contact hole by etching. The projection of the bottom surface of the contact hole onto the substrate is within the circumference of the projected profile of the contact stopper film formed on the top and side surface of the columnar semiconductor layer onto the substrate.Type: ApplicationFiled: August 18, 2010Publication date: February 24, 2011Applicant: UNISANTIS ELECTRONICS (JAPAN) LTD.Inventors: Fujio MASUOKA, Shintaro ARAI, Hiroki NAKAMURA, Tomohiko KUDO, R. Ramana MURTHY, Nansheng SHEN, Kavitha Devi BUDDHARAJU, Navab SINGH
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Publication number: 20110018053Abstract: A memory cell is provided. The memory cell comprises a first wire shaped channel structure; and a charge trapping structure surrounding the perimeter surface of the first wire shaped channel structure, the charge trapping structure comprising two charge trapping partial to structures, wherein each charge trapping partial structure is formed of a different material capable of storing electrical charges. Methods of manufacturing the memory cell are also provided.Type: ApplicationFiled: December 7, 2007Publication date: January 27, 2011Applicant: Agency For Science, Technology And ResearchInventors: Guo Qiang Patrick Lo, Jia Fu, Mingbin Yu, Navab Singh
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Publication number: 20110012090Abstract: A silicon-germanium nanowire structure arranged on a support substrate is disclosed, The silicon-germanium nanowire structure includes at least one germanium-containing supporting portion arranged on the support substrate, at least one germanium-containing nanowire disposed above the support substrate and arranged adjacent the at least one germanium-containing supporting portion, wherein germanium concentration of the at least one germanium-containing nanowire is higher than the at least one germanium-containing supporting portion. A transistor comprising the silicon-germanium nanowire structure arranged on a support substrate is also provided. A method of forming a silicon-germanium nanowire structure arranged on a support substrate and a method of forming a transistor comprising forming the silicon-germanium nanowire structure arranged on a support substrate are also disclosed.Type: ApplicationFiled: December 7, 2007Publication date: January 20, 2011Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Navab Singh, Jiang Yu, Guo Qiang Patrick Lo
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Publication number: 20100264485Abstract: This invention provides a method of manufacturing a semiconductor device, which comprises the steps of: forming a first columnar semiconductor layer on a first flat semiconductor layer; forming a first semiconductor layer of a second conductive type in a lower portion of the first columnar semiconductor layer; forming a first insulating film around a lower sidewall of the first columnar silicon layer; forming a gate insulating film and a gate electrode around the first columnar silicon layer; forming a sidewall-shaped second insulating film to surround an upper sidewall of the first columnar silicon layer; forming a semiconductor layer of a first conductive type between the first semiconductor layer of the second conductive type and a second semiconductor layer of the second conductive type; and forming a metal-semiconductor compound on an upper surface of the first semiconductor layer of the second conductive type.Type: ApplicationFiled: April 16, 2010Publication date: October 21, 2010Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Navab Singh, Kavitha Devi Buddharaju, Shen Nansheng, Rukmani Devi Sayanthan