Abstract: A system for releasing analytes contained within a sample. The system comprises a housing enclosing an interior space. The system additionally comprises a sample holder having at least one receptacle configured to receive a sample containing analytes bound within the sample. The system further includes at least one light emitting diode configured to generate light sufficient to separate photo-cleavable bonds binding the analytes within the sample.

Abstract: A device to predict failure in a power supply includes a converter circuit configured to generate a regulated output voltage. The device additionally includes a first feedback circuit to generate a first feedback voltage proportional to the regulated output voltage and a second feedback circuit to generate a second feedback voltage based on the regulated output voltage. The second feedback circuit includes a voltage sampling circuit to detect the regulated output voltage, a correction circuit to generate a correction signal responsive to a voltage difference between the regulated output voltage and a specified output voltage, a reference circuit to obtain a specified correction signal to apply to the power supply, a comparator circuit to determine whether a difference between the generated correction signal and the specified correction signal exceeds a threshold signal value, and an alerting circuit to generate an alert signal responsive to the determination.

Abstract: A method for automating performance evaluation of a test object detection system includes providing at least one frame of image data to the test object detection system, processing the image data via an image processor of the test object detection system, and receiving, from the test object detection system, a list of objects detected by the test object detection system in the at least one frame of image data. The frame of image data is provided to a validation object detection system, and a list of objects detected by the validation object detection system is received from the validation object detection system. The list of objects detected by the test object detection system is compared to the list of objects detected by the validation object detection system and discrepancies are determined between the lists. The determined discrepancies between the lists of objects detected are reported.

Abstract: A device to predict failure in a power supply includes a converter circuit configured to generate a regulated output voltage. The device additionally includes a first feedback circuit to generate a first feedback voltage proportional to the regulated output voltage and a second feedback circuit to generate a second feedback voltage based on the regulated output voltage. The second feedback circuit includes a voltage sampling circuit to detect the regulated output voltage, a correction circuit to generate a correction signal responsive to a voltage difference between the regulated output voltage and a specified output voltage, a reference circuit to obtain a specified correction signal to apply to the power supply, a comparator circuit to determine whether a difference between the generated correction signal and the specified correction signal exceeds a threshold signal value, and an alerting circuit to generate an alert signal responsive to the determination.

Abstract: A method for automating performance evaluation of a test object detection system includes providing at least one frame of image data to the test object detection system, processing the image data via an image processor of the test object detection system, and receiving, from the test object detection system, a list of objects detected by the test object detection system in the at least one frame of image data. The frame of image data is provided to a validation object detection system, and a list of objects detected by the validation object detection system is received from the validation object detection system. The list of objects detected by the test object detection system is compared to the list of objects detected by the validation object detection system and discrepancies are determined between the lists. The determined discrepancies between the lists of objects detected are reported.

Abstract: A system, method, and computer program product are provided for providing seamless data access from different internet service providers. In operation, a master modem receives a ping from a device for requesting an encrypted key associated with an internet session corresponding to one of a plurality of Internet Service Providers (ISPs). The master modem authenticates the device and responds with the encrypted key. The master modem notifies an Internet Service Provider (ISP) system associated with the internet session with the encrypted key before beginning the internet session with the device. The ISP system verifies parameters to determine whether to allow the session to begin, in response to the notifying. The master modem receives authorization to begin the internet session from the ISP system. The master modem sets a port and speed associated with the master modem to aid in maintaining Quality of Service (QoS) for the internet session.

Abstract: An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.

Abstract: An FFT device for performing a Fast Fourier Transform (FFT) is described. The FFT device comprises: a control unit arranged to control a sequence of transformation rounds; and a coefficient unit for providing transformation data; and a transformation unit arranged to receive the transformation data and to perform the respective linear transformation on the basis of the transformation data. The coefficient unit comprises or is integrated in a Random Access Memory (RAM) unit, the RAM unit comprising a set of memory blocks. The set of memory blocks comprises: a subset of window memory blocks or a subset of window-FFT memory blocks. The set of memory blocks further comprises a subset of FFT memory blocks providing a set of twiddle coefficients or a reduced set of twiddle coefficients.

Abstract: An FFT device for performing a Fast Fourier Transform (FFT) of an operand vector of length N is described. The FFT device comprises a control unit, a coefficient unit, and a transformation unit. The control unit controls a sequence of transformation rounds, the transformation rounds including two or more FFT rounds and further including or not including a window round. The control unit also maintains configuration data indicating for each of said transformation rounds whether the respective transformation round is an FFT round, a window-FFT round, or a window round. The coefficient unit provides transformation data. The transformation unit is arranged to receive the transformation data and to perform the respective linear transformation on the basis of the transformation data. A method for performing a Fast Fourier Transform is described as well.

Abstract: A system comprises a plurality of power supplies, wherein a power supply provides a supply voltage rail to a voltage domain of the system; a plurality of power supply voltage sequencer devices electrically coupled to multiple power supplies of the plurality of power supplies, wherein a voltage sequencer device is configured to activate the multiple power supplies in a specified sequence; and a bus electrically coupled to the plurality of power supply voltage sequencer devices, wherein the bus is configured to communicate state information of the plurality of power supply voltage sequencer devices.

Abstract: Methods and compositions are provided which employ a silencing element that, when ingested by a pest, such as a Pentatomidae plant pest, decrease the expression of a target sequence in the pest. The present invention provides various target polynucleotides set forth in any one of SEQ ID NOS: 6-12, 18-40 or active variants and fragments thereof, wherein a decrease in expression of one or more the sequences in the target pest controls the pest (i.e., has insecticidal activity). Plants, plant part, bacteria and other host cells comprising the silencing elements or an active variant or fragment thereof of the invention are also provided.

Abstract: A system for performing a data transaction between a memory and a master via a bus based on a strobe signal. The memory includes at least one memory bank having first and second cuts. The data transaction is either a read transaction or a write transaction. The system includes an input and output interface in communication with the master for receiving a data transaction request, an identifying unit that identifies a type of the data transaction, a control unit that selectively enables at least one of the first and second cuts based on the data transaction type, and a data processing unit that processes data to be read from or written to the enabled cut based on the data transaction type.

Abstract: An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.

Abstract: An online marketplace of digital goods is provided. A digital good proposed to be listed in the marketplace is received, where the source code for the received digital good includes scripting language code. The source code of the received digital good is rewritten to include tracking code to track behavior of the received digital good during execution of the re-written digital good, and the rewritten digital good is executed in a browser run by one or more processors of a computer system. One or more processors of the computer system automatically determine, based on evaluation of results of executing the re-written digital good, whether the digital good violates one or more predetermined conditions. Based on the determination of whether the digital good violates one or more of the predetermined conditions, an automatic determination is made whether to list the received digital good in the marketplace.

Abstract: A system for performing a data transaction between a memory and a master via a bus based on a strobe signal. The memory includes at least one memory bank having first and second cuts. The data transaction is either a read transaction or a write transaction. The system includes an input and output interface in communication with the master for receiving a data transaction request, an identifying unit that identifies a type of the data transaction, a control unit that selectively enables at least one of the first and second cuts based on the data transaction type, and a data processing unit that processes data to be read from or written to the enabled cut based on the data transaction type.

Abstract: A system comprises a plurality of power supplies, wherein a power supply provides a supply voltage rail to a voltage domain of the system; a plurality of power supply voltage sequencer devices electrically coupled to multiple power supplies of the plurality of power supplies, wherein a voltage sequencer device is configured to activate the multiple power supplies in a specified sequence; and a bus electrically coupled to the plurality of power supply voltage sequencer devices, wherein the bus is configured to communicate state information of the plurality of power supply voltage sequencer devices.

Abstract: A digital good offered for downloading from a first computing system to a client computing device for execution by a browser executing on the client is identified. The digital good is received at a third computing system, where source code for the received digital good includes scripting language code. The code is re-written to include tracking code to track behavior of the digital good during execution of the digital good, and the re-written digital good is executed in a browser run by the third computing system. Based on evaluation of results of executing the re-written digital good, it is automatically determined, by the third computer system, whether the digital good violates one or more predetermined conditions, and based on the determination of whether the digital good violates a predetermined conditions, it is automatically determined whether to discourage downloading the digital good to, or executing the digital good by, the client.

Abstract: Techniques for selecting a digital image are disclosed. The techniques may include receiving a first set of digital images, analyzing the first set of digital images to extract first image features from each of the first set of digital images, accessing a user profile, comparing the extracted first image features to a preset list of image features, ranking each digital image of the first set, selecting each digital image having a ranking that exceeds a threshold, assigning a category to each selected digital image based on a comparison of each selected digital image to a category database of digital image categories, displaying each selected digital image with the assigned category, receiving an input from the user in response to the displaying, updating the user profile and the category database based on the input, and selecting at least one subsequent digital image based on the updated user profile and category database.

Abstract: A memory controller that implements an interleaving and arbitration scheme includes an address decoder that selects a memory bank for an access request based on a set of address least significant bits included in the access request. A core requiring sequential access to memory is routed to consecutive memory banks of the memory for consecutive access requests. When multiple cores request access to the same memory bank, an arbiter determines an access sequence for the cores. The arbiter can modify the access sequence without significantly increasing the complexity of the memory controller. The address decoder determines whether the selected memory banks are available and also whether an access request is a wide access request, in which case it selects two consecutive memory banks.

Abstract: A memory controller that implements an interleaving and arbitration scheme includes an address decoder that selects a memory bank for an access request based on a set of address least significant bits included in the access request. A core requiring sequential access to memory is routed to consecutive memory banks of the memory for consecutive access requests. When multiple cores request access to the same memory bank, an arbiter determines an access sequence for the cores. The arbiter can modify the access sequence without significantly increasing the complexity of the memory controller. The address decoder determines whether the selected memory banks are available and also whether an access request is a wide access request, in which case it selects two consecutive memory banks.