Abstract: A calibrated digital-to-analog converter (DAC) is provided that includes a DAC having an interpolation circuit (40) and delta-sigma converter (44). The output of the delta-sigma converter (44) is input to a one-bit DAC (48) and the output thereof filtered by an analog low pass filter section (50). During a calibration procedure, a calibrated analog-to-digital converter (ADC) (22) is utilized that is operable to receive the analog output of the DAC with a "0" value input thereto through a multiplexer (58). The output of the ADC (22) represents the inherent error in the delta-sigma converter (44) and the analog filter section (50). This is stored in a register (62). In a second step of the operation, the contents of the register (62) are input through the interpolation circuit for interpolation thereof and storage in an offset register/latch circuit (56).