Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

Abstract: One example provides an enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer over the substrate, a Group IIIA-N barrier layer over the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A gate stack is located between source and drain contacts to the active layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on a p-GaN layer located on the barrier layer.

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

Abstract: One example provides an enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer over the substrate, a Group IIIA-N barrier layer over the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A gate stack is located between source and drain contacts to the active layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on a p-GaN layer located on the barrier layer.

Abstract: An enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer on the substrate, a Group IIIA-N barrier layer on the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A p-GaN layer is on the barrier layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on the p-GaN layer. A gate electrode is over the n-GaN layer. A drain having a drain contact is on the barrier layer to provide contact to the active layer, and a source having a source contact is on the barrier layer provides contact to the active layer. The tunnel diode provides a gate contact to eliminate the need to form a gate contact directly to the p-GaN layer.

Abstract: In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.

Abstract: An enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer on the substrate, a Group IIIA-N barrier layer on the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A p-GaN layer is on the barrier layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on the p-GaN layer. A gate electrode is over the n-GaN layer. A drain having a drain contact is on the barrier layer to provide contact to the active layer, and a source having a source contact is on the barrier layer provides contact to the active layer. The tunnel diode provides a gate contact to eliminate the need to form a gate contact directly to the p-GaN layer.

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

Abstract: A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa includes a drift region and a body region. The width of the mesa is in the order of quantum well dimension at the interface between the gate insulator regions and the body regions The TMOSFET also includes a plurality of gate insulator regions disposed between the gate regions and the body regions, drift regions, and drain region. The thickness of the gate insulator regions between the gate regions and the drain region results in a gate-to-drain electric field in an OFF-state that is substantially lateral aiding to deplete the charge in the drift regions.

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

Abstract: In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.