Patents by Inventor Navneet Gupta

Navneet Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220027541
    Abstract: Microelectronic circuit com-prises a plurality of logic units and register circuits, arranged into a plu-rality of processing paths, and a plu-rality of monitoring units associated with respective ones of said processing paths. Each of said monitoring units is configured to produce an observation signal as a response to anomalous opera-tion of the respective processing path. Each of said plurality of logic units belongs to one of a plurality of delay classes according to an amount of delay that it is likely to generate. Said de-lay classes comprise first, second, and third classes, of which the first class covers logic units that are likely to generate longest delays, the second class covers logic units that are likely to generate shorter delays than said first class, and the third class covers logic units that are likely to generate shorter delays than said second class. At least some of said plurality of pro-cessing paths comprise logic units be-longing to said second class but are without monitoring units.
    Type: Application
    Filed: November 27, 2018
    Publication date: January 27, 2022
    Applicant: MINIMA PROCESSOR OY
    Inventor: Navneet GUPTA
  • Publication number: 20220021390
    Abstract: A microelectronic circuit comprises a plurality of logic units and register circuits arranged into a plurality of processing paths. At least one monitor circuit (404) is associated with a first register circuit (301), said monitor circuit (404) being configured to produce a timing event observation signal as a response to a change in a digital value at an input (D) of the first register circuit (301) that took place later than an allowable time limit defined by a triggering signal (CP) to said first register circuit (301). A first processing path goes through a first logic unit (501) to said first register circuit (301) and is a delay critical processing path due to an amount of delay that it is likely to generate. The microelectronic circuit comprises a controllable data event injection point (503) for controllably generating a change of a digital value propagating to said first logic unit (501) irrespective of what other data is processed on said first processing path.
    Type: Application
    Filed: December 5, 2018
    Publication date: January 20, 2022
    Applicant: MINIMA PROCESSOR OY
    Inventor: Navneet GUPTA
  • Publication number: 20210318377
    Abstract: The performance of a microelectronic circuit can be configured by making an operating parameter assume an operating parameter value. An operating method comprises selectively setting the microelectronic circuit into a test mode that differs from a normal operating mode of the microelectronic circuit, and utilizing said test mode to input test input signals consisting of test input values into one or more adaptive processing paths within the microelectronic circuit. An adaptive processing path comprises processing logic and register circuits configured to produce output values from input values input to them. The performance of such an adaptive processing path can be configured by making an operating parameter assume an operating parameter value.
    Type: Application
    Filed: October 16, 2018
    Publication date: October 14, 2021
    Inventors: Lauri KOSKINEN, Navneet GUPTA, Jesse SIMONSSON
  • Publication number: 20200389155
    Abstract: A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal is also received, a triggering edge of which defines an allowable time limit before which a digital value must be available at said data input to become available for said subsequent circuit element. Between first and second pulse-enabled subregister stages, an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit are used to ensure passing a valid internal digital value to the second pulse-enabled subregister stage. Said second pulse-enabled subregister stage makes said valid internal digital value available for said subsequent circuit element.
    Type: Application
    Filed: December 1, 2017
    Publication date: December 10, 2020
    Applicant: MINIMA PROCESSOR OY
    Inventor: Navneet GUPTA
  • Publication number: 20200389156
    Abstract: Digital values obtained from an output of a preceding circuit element are temporarily stored and made available for a subsequent circuit element at a controlled moment of time. A digital value is received for temporary storage, as well as a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become available for said subsequent circuit element. A sequence of first and second pulse-enabled subregister stages is used to temporarily store said digital value. Said triggering signal is provided to said first pulse-enabled subregister stage delayed with respect to the triggering signal received by said second pulse-enabled subregister stage. The length of the delay is a fraction of a cycle of the triggering signal.
    Type: Application
    Filed: December 1, 2017
    Publication date: December 10, 2020
    Applicant: MINIMA PROCESSOR OY
    Inventor: Navneet GUPTA
  • Publication number: 20190080761
    Abstract: A CAM memory cell including: a latch including N first TFETs serially connected one to the other between two supply electric potentials such that each source and drain of each first TFETs is connected either to one supply electric potentials or to the source or drain of another first TFETs, and wherein one electric potentials is applied on the gate of each first TFETs which are in reverse bias VDS and forward bias VGS, with N?2; an output block connected to N?1 storage nodes formed at connection points between the first TFETs, and configured to read a data stored in the storage nodes and/or to output a value representative of a matching or mismatching between a search data and the stored data; a write block configured to apply a data to be stored in the storage nodes.
    Type: Application
    Filed: March 13, 2017
    Publication date: March 14, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Adam MAKOSIEJ, Amara AMARA, Costin ANGHEL, Navneet GUPTA
  • Patent number: 10110203
    Abstract: Tri-state inverter includes a n-TFET and a p-TFET, the drain of the n-TFET being connected to the drain of the p-TFET and to an output of the tri-state inverter, the gates of the n-TFET and p-TFET being connected to an input of the tri-state inverter, and a control circuit able to apply a first control voltage on the source of the n-TFET and a second control voltage on the source of the p-TFET, the values of the first and second control voltages being positive or zero, wherein, when the tri-state inverter is intended to work as an inverter, the value of the first control voltage is lower than the value of the second control voltage, and when the tri-state inverter is intended to be tri-stated, the value of the first control voltage is higher than the value of the second control voltage.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: October 23, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Navneet Gupta, Adam Makosiej, Costin Anghel, Amara Amara
  • Publication number: 20180268890
    Abstract: Memory latch comprising: a TFET; a capacitor; a storage node formed by the connection of a first terminal of the capacitor to a first electrode of the TFET; a control circuit configured to supply a first electric potential on a second terminal of the capacitor, a second electric potential on the gate of the TFET and a third electric potential on a second electrode of the TFET, such that: when the stored potential is low, the TFET is reverse biased with a conduction current obtained by band-to-band tunneling with a value higher than a capacitor leakage current; when the stored potential is high, the TFET is reverse biased with an OFF state current value less than the capacitor leakage current.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 20, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Navneet Gupta, Amara Amara, Costin Anghel, Adam Makosiej
  • Patent number: 10079056
    Abstract: A SRAM memory bit cell is provided that includes a n-TFET and a p-TFET; a storage node formed by the connection of a first electrode of the n-TFET to a first electrode of the p-TFET (drains or sources); and a control circuit able to apply supply voltages on second electrodes of the n-TFET and p-TFET (sources or drains). The control circuit is configured to provide, during a retention mode, supply and bias voltages reverse biasing the n-TFET and p-TFET in a state wherein a conduction current is obtained by band-to-band tunneling in the n-TFET and p TFET. The control circuit is further configured to provide, during a writing of a bit, supply and bias voltages forward biasing the n-TFET and p-TFET and such that one of the n-TFET and p-TFET is in OFF state and that the other of the n-TFET and p-TFET is in ON state.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: September 18, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Navneet Gupta, Adam Makosiej, Costin Anghel, Amara Amara
  • Publication number: 20180012222
    Abstract: An embodiment of the invention may include a method, computer program product and system for transaction authentication. The embodiment may include receiving, by a mobile device from a network server via a wireless access point using a medium-range wireless communication protocol, an indication corresponding to a transaction to execute. The embodiment may include displaying a graphical interface element having an indication of approval to initiate the transaction to execute from a user based on receiving the indication. The embodiment may include authorizing the transaction to execute for a period of time based on receiving the indication of approval to initiate the transaction to execute. The embodiment may include detecting within the period of time, from a point of sale device using a short-range wireless communication protocol, a mobile payment method associated with the transaction to execute. The embodiment may include initiating the transaction based on detecting the mobile payment method.
    Type: Application
    Filed: July 11, 2016
    Publication date: January 11, 2018
    Inventors: Shawn L. Berger, Navneet Gupta, Rick A. Hamilton, II, Shawn P. Mullen, Nithya A. Renganathan, Karen M. Siles
  • Patent number: 9860066
    Abstract: Embodiments of the present invention utilize a data hash and an associated geotag for authentication of geolocation policies for data object storage in a cloud system. The geotag may be an alphanumeric identifier such as a city name, postal (ZIP) code, and/or latitude-longitude pair. Embodiments include a post-authenticate process, in which, after a data object is retrieved from a BMS, the geographic location of the source is confirmed to ensure the location policies have not been violated. Additionally, embodiments include a pre-authenticate process, in which, prior to storing a data object in a BMS, the geographic location of the BMS that is to receive the data object is confirmed to ensure the location policies will not be violated. Embodiments may use pre-authenticate, post-authenticate, or both pre-authenticate and post-authenticate, in order to implement and verify the location policies.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Shawn L. Berger, Navneet Gupta, Rick A. Hamilton, II, Shawn P. Mullen, Nithya A. Renganathan, Karen M. Siles
  • Publication number: 20170263308
    Abstract: SRAM memory bit cell comprising: a n-TFET and a p-TFET; a storage node formed by the connection of a first electrode of the n-TFET to a first electrode of the p-TFET (drains or sources); a control circuit able to apply supply voltages on second electrodes of the n-TFET and p-TFET (sources or drains); wherein the control circuit is configured to provide: during a retention mode, supply and bias voltages reverse biasing the n-TFET and p-TFET in a state wherein a conduction current is obtained by band-to-band tunneling in the n-TFET and p-TFET; during a writing of a bit, supply and bias voltages forward biasing the n-TFET and p-TFET and such that one of the n-TFET and p-TFET is in OFF state and that the other of the n-TFET and p-TFET is in ON state.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 14, 2017
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Navneet GUPTA, Adam MAKOSIEJ, Costin ANGHEL, Amara AMARA
  • Publication number: 20170264275
    Abstract: Tri-state inverter comprising: a n-TFET and a p-TFET, the drain of the n-TFET being connected to the drain of the p-TFET and to an output of the tri-state inverter, the gates of the n-TFET and p-TFET being connected to an input of the tri-state inverter; a control circuit able to apply a first control voltage on the source of the n-TFET and a second control voltage on the source of the p-TFET, the values of the first and second control voltages being positive or zero; and wherein, when the tri-state inverter is intended to work as an inverter, the value of the first control voltage is lower than the value of the second control voltage, and when the tri-state inverter is intended to be tri-stated, the value of the first control voltage is higher than the value of the second control voltage.
    Type: Application
    Filed: March 9, 2017
    Publication date: September 14, 2017
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Navneet GUPTA, Adam MAKOSIEJ, Costin ANGHEL, Amara AMARA
  • Patent number: 9679649
    Abstract: A content addressable memory having at least one CAM cell including first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bitline, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bitline, the second transistor being controlled by a second control signal; and a control circuit adapted to perform a CAM read operation by pre-charging the bitline to a first voltage level, and then selectively activating either the first or second transistor based on a bit of input data.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: June 13, 2017
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Navneet Gupta, Adam Makosiej, Costin Anghel, Amara Amara, Olivier Thomas
  • Publication number: 20170141921
    Abstract: Embodiments of the present invention utilize a data hash and an associated geotag for authentication of geolocation policies for data object storage in a cloud system. The geotag may be an alphanumeric identifier such as a city name, postal (ZIP) code, and/or latitude-longitude pair. Embodiments include a post-authenticate process, in which, after a data object is retrieved from a BMS, the geographic location of the source is confirmed to ensure the location policies have not been violated. Additionally, embodiments include a pre-authenticate process, in which, prior to storing a data object in a BMS, the geographic location of the BMS that is to receive the data object is confirmed to ensure the location policies will not be violated. Embodiments may use pre-authenticate, post-authenticate, or both pre-authenticate and post-authenticate, in order to implement and verify the location policies.
    Type: Application
    Filed: November 12, 2015
    Publication date: May 18, 2017
    Inventors: Shawn L. Berger, Navneet Gupta, Rick A. Hamilton, II, Shawn P. Mullen, Nithya A. Renganathan, Karen M. Siles
  • Publication number: 20170133092
    Abstract: A content addressable memory having at least one CAM cell including first and second inverters cross-coupled between first and second storage nodes; a first transistor coupling the first storage node to a bitline, the first transistor being controlled by a first control signal; a second transistor coupling the second storage node to the bitline, the second transistor being controlled by a second control signal; and a control circuit adapted to perform a CAM read operation by pre-charging the bitline to a first voltage level, and then selectively activating either the first or second transistor based on a bit of input data.
    Type: Application
    Filed: November 3, 2016
    Publication date: May 11, 2017
    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Navneet Gupta, Adam Makosiej, Costin Anghel, Amara Amara, Olivier Thomas
  • Patent number: 8737144
    Abstract: An embodiment of a sense amplifier includes a sense circuit and a monitor circuit. The sense circuit is configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data, and the monitor circuit is configured to indicate a reliability of the second signal. The monitor circuit allows, for example, adjusting a parameter of a memory in which the memory cell is disposed to increase the read accuracy, and may also allow recognizing and correcting an error due to an invalid second signal.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 27, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Navneet Gupta, Prashant Dubey, ShaileshKumar Pathak, Kaushik Saha, Ashish Kumar, R Sai Krishna
  • Patent number: 8624623
    Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: January 7, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Navneet Gupta, Prashant Dubey, Kaushik Saha, AtulKumar Kashyap
  • Publication number: 20130169360
    Abstract: According to an embodiment, an apparatus includes: a first node configured to receive a data input signal of a data latch; a second node configured to receive a data output signal of the data latch; process and hold circuitry configured to process a difference between a value of the data input signal received at the first node and a value of the data output signal received at the second node and hold respective values at the first and second nodes responsive to the difference; and comparison circuitry configured to compare the value held at the first node and a value of the data output signal of the data latch; wherein the process and hold circuitry is configured to be biased toward the signal received at one of the first node and the second node.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Navneet GUPTA, Prashant DUBEY, Kaushik SAHA, AtulKumar KASHYAP
  • Publication number: 20130170306
    Abstract: An embodiment of a sense amplifier includes a sense circuit and a monitor circuit. The sense circuit is configured to convert a first signal that corresponds to data stored in a memory cell into a second signal that corresponds to the data, and the monitor circuit is configured to indicate a reliability of the second signal. The monitor circuit allows, for example, adjusting a parameter of a memory in which the memory cell is disposed to increase the read accuracy, and may also allow recognizing and correcting an error due to an invalid second signal.
    Type: Application
    Filed: December 29, 2011
    Publication date: July 4, 2013
    Applicant: STMICROELECTRONICS PVT. LTD.
    Inventors: Navneet GUPTA, Prashant DUBEY, ShaileshKumar PATHAK, Kaushik SAHA, Ashish KUMAR, R Sai KRISHNA