Patents by Inventor Nazir Ahmad
Nazir Ahmad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7211901Abstract: A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool.Type: GrantFiled: June 3, 2005Date of Patent: May 1, 2007Assignee: ChipPAC, Inc.Inventors: Young-Do Kweon, Rajendra D. Pendse, Nazir Ahmad, Kyung-Moon Kim
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Publication number: 20060255474Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points. Also, a flip chip package is made by the method. In some embodiments the metallurgical connection includes an alloy of gold and tin at the interface between the bumps and the interconnect points.Type: ApplicationFiled: June 1, 2006Publication date: November 16, 2006Applicant: ChipPAC, IncInventors: Nazir Ahmad, Young-Do Kweon, Samuel Tam, Kyung-Moon Kim, Rajendra Pendse
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Publication number: 20050218515Abstract: A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool.Type: ApplicationFiled: June 3, 2005Publication date: October 6, 2005Applicant: ChipPAC, IncInventors: Young-Do Kweon, Rajendra Pendse, Nazir Ahmad, Kyung-Moon Kim
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Publication number: 20050221535Abstract: A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool.Type: ApplicationFiled: June 3, 2005Publication date: October 6, 2005Applicant: ChipPAC, Inc.Inventors: Young-Do Kweon, Rajendra Pendse, Nazir Ahmad, Kyung-Moon Kim
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Patent number: 6940178Abstract: A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool.Type: GrantFiled: February 22, 2002Date of Patent: September 6, 2005Assignee: ChipPAC, Inc.Inventors: Young-Do Kweon, Rajendra Pendse, Nazir Ahmad, Kyung-Moon Kim
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Publication number: 20040222440Abstract: A flip chip package is formed by a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material. Accordingly the connections are capable of carrying very high current, and display good long-term reliability as compared to ACA or ICA particulate interconnects. Moreover the solid-state bond technique does not entail a melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries, typically as low as 70 micrometers pitch.Type: ApplicationFiled: May 4, 2004Publication date: November 11, 2004Applicant: ChipPAC, IncInventors: Rajendra Pendse, Nazir Ahmad, Andrea Chen, Kyung-Moon Kim, Young Do Kweon, Samuel Tam
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Patent number: 6737295Abstract: A flip chip package is formed by a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material nor any melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries. In another aspect, the space between the surface of the integrated circuit chip and the subjacent surface of the package substrate is filled with a patterned adhesive structure, which consists of one or more adhesive materials that are deployed in a specified pattern in relation to the positions of the second level interconnections between the package and the printed circuit board.Type: GrantFiled: February 22, 2002Date of Patent: May 18, 2004Assignee: ChipPAC, Inc.Inventors: Rajendra Pendse, Nazir Ahmad, Andrea Chen, Kyung-Moon Kim, Young Do Kweon, Samuel Tam
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Patent number: 6514296Abstract: A dry preunit (10), includes a plurality of cells (110, 112, 114) in a true bipolar configuration, which are stacked and bonded together, to impart to the device an integral and unitary construction. Each cell (114) includes two electrically conductive electrodes (111A, 111B) that are spaced apart by a predetermined distance. The cell (114) also includes two identical dielectric gaskets (121, 123) that are interposed, in registration with each other, between the electrodes (111A, 11B), for separating and electrically insulating these electrodes. When the electrodes (111A, 111B), and the gaskets (121, 123) are bonded together, at least one fill gap (130) is formed for each cell. Each cell (114) also includes a porous and conductive coating layer (119, 120) that is formed on one surface of each electrode. The coating layer (119) includes a set of closely spaced-apart peripheral microprotrusions (125), and a set of distally spaced-apart central microprotrusions (127).Type: GrantFiled: October 19, 1998Date of Patent: February 4, 2003Assignee: Pacific ShinFu Technologies Co., Ltd.Inventors: K. C. Tsai, Gary E. Mason, Mark L. Goodwin, Nazir Ahmad, Davy Wu, Douglas Cromack, Robert R. Tong, James M. Poplett, Ronald L. Anderson, James P. Nelson, Alan B. McEwen
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Publication number: 20020151228Abstract: A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool.Type: ApplicationFiled: February 22, 2002Publication date: October 17, 2002Applicant: ChipPAC, Inc.Inventors: Young-Do Kweon, Rajendra Pendse, Nazir Ahmad, Kyung-Moon Kim
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Publication number: 20020151189Abstract: A flip chip package is formed by a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material. Accordingly the connections are capable of carrying very high current, and display good long-term reliability as compared to ACA or ICA particulate interconnects. Moreover the solid-state bond technique does not entail a melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries, typically as low as 70 micrometers pitch.Type: ApplicationFiled: February 22, 2002Publication date: October 17, 2002Applicant: ChipPAC, Inc.Inventors: Rajendra Pendse, Nazir Ahmad, Andrea Chen, Kyung-Moon Kim, Young-Do Kweon, Samuel Tam
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Publication number: 20020014702Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points. Also, a flip chip package is made by the method. In some embodiments the metallurgical connection includes an alloy of gold and tin at the interface between the bumps and the interconnect points.Type: ApplicationFiled: March 9, 2001Publication date: February 7, 2002Inventors: Nazir Ahmad, Young-Do Kweon, Samuel Tam, Kyung-Moon Kim, Rajendra D. Pendse
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Patent number: 5867363Abstract: A dry preunit (10), includes a plurality of cells (110, 112, 114) in a true bipolar configuration, which are stacked and bonded together, to impart to the device an integral and unitary construction. Each cell (114) includes two electrically conductive electrodes (111A, 111B) that are spaced apart by a predetermined distance. The cell (114) also includes two identical dielectric gaskets (121, 123) that are interposed, in registration with each other, between the electrodes (111A, 111B), for separating and electrically insulating these electrodes. When the electrodes (111A, 111B), and the gaskets (121, 123) are bonded together, at least one fill gap (130) is formed for each cell. Each cell (114) also includes a porous and conductive coating layer (119, 120) that is formed on one surface of each electrode. The coating layer (119) includes a set of closely spaced-apart peripheral microprotrusions (125), and a set of distally spaced-apart central microprotrusions (127).Type: GrantFiled: March 30, 1994Date of Patent: February 2, 1999Assignee: Pinnacle Research Institute, Inc.Inventors: K. C. Tsai, Gary E. Mason, Mark L. Goodwin, Nazir Ahmad, Davy Wu, Douglas Cromack, Robert R. Tong, James M. Poplett, Ronald L. Anderson, James P. Nelson, Alan B. McEwen
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Patent number: 5800857Abstract: A dry preunit (10), includes a plurality of cells (110, 112, 114) in a true bipolar configuration, which are stacked and bonded together, to impart to the device an integral and unitary construction. Each cell (114) includes two electrically conductive electrodes (111A, 111B) that are spaced apart by a predetermined distance. The cell (114) also includes two identical dielectric gaskets (121, 123) that are interposed, in registration with each other, between the electrodes (111A, 111B), for separating and electrically insulating these electrodes. When the electrodes (111A, 111B), and the gaskets (121, 123) are bonded together, at least one fill gap (130) is formed for each cell. Each cell (114) also includes a porous and conductive coating layer (119, 120) that is formed on one surface of each electrode. The coating layer (119) includes a set of closely spaced-apart peripheral microprotrusions (125), and a set of distally spaced-apart central microprotrusions (127).Type: GrantFiled: September 30, 1996Date of Patent: September 1, 1998Assignee: Pinnacle Research Institute, Inc.Inventors: Nazir Ahmad, Keh-Chi Tsai