Abstract: Systems and methods for detection of defects on a magnetic storage medium. The method comprises: (1) receiving incoming detected data generated by reading information recorded on a storage medium, (2) identifying the defects in the storage medium based on comparison between the incoming detected data and a data pattern wherein the data pattern is predetermined; and (3) storing location information indicative of locations of the defects on the storage medium.

Abstract: An ERSEC system that applies a level of error correction that is inversely related to susceptibility to error as indicated by a signal-to-noise ratio (SNR) profile of a channel. The SNR profile is estimated, detected or retrieved from an external source. The ERSEC system is used with any channel for which the SNRs can vary spatially, temporally or both.

Abstract: Systems and methods are provided for decoding data. A decoder retrieves data related to a symbol and identifies a plurality of candidate values for the symbol. The decoder determines a distance between each of the plurality of candidate values and a reference value associated with the symbol to obtain a plurality of distances, and the decoder determines whether to update a value of the symbol based at least in part on the plurality of distances.

Abstract: Systems and methods are provided for decoding data using hard decisions and erasures. Circuitry receives data from each of a plurality of variable nodes which correspond to bits of data being decoded. Each variable node stores one of at least three values. The circuitry determines processes the values received from the plurality of variable nodes according to a set of processing rules. The processing rules are used to determine a condition related to the values stored by the plurality of variable nodes. The circuitry stores an indication of the stored condition at a check node.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

Abstract: Some of the embodiments of the present disclosure provide a system, device and a method performing N read cycles on a plurality of memory cells of a memory sector, wherein N is an integer greater than one; constructing (N+1) bin histograms based at least in part on performing the N read cycles; identifying a shortest bin histogram of the (N+1) bin histograms; and based on a height of the shortest histogram, assigning a log-likelihood ratio (LLR) to the shortest bin histogram. Other embodiments are also described and claimed.

Abstract: Systems and methods are provided for enhancing the performance and throughput of a low-density parity check (LDPC) decoder. In some embodiments, the enhanced performance and throughput may be achieved by detecting and correcting near-codewords before the decoder iterates up to a predetermined number of iterations. In some embodiments, a corrector runs concurrently with the decoder to correct a near-codeword when the near-codeword is detected. In alternate embodiments, the corrector is active while the decoder is not active. Both embodiments allow for on-the-fly codeword error corrections that improve the performance (e.g., reducing the number of errors) without decreasing the throughput of the decoder.

Abstract: Systems and methods are provided for encoding data based on an LDPC code using various inversion mechanisms to obtain parity bits. In some embodiments, an LDPC encoder may compute parity bits using a speculative recursion and correction mechanism. In these embodiments, the LDPC encoder may initiate a recursion using at least one speculative value in place of the actual value for a parity component. The speculative values may then be corrected using a correction factor. In other embodiments, an LDPC encoder is provided that can perform a blockwise inversion mechanism. This mechanism may be used on LDPC codes with parity check matrices having a parity portion composed partially of a large triangular matrix. In still other embodiments, a generic LDPC encoder is provided. The generic LDPC encoder can implement a variety of different encoding techniques, such as different inversion mechanisms, and may be processor-based or finite state machine-based.

Abstract: Systems and methods for jointly optimizing various parameters of an error-correction code (e.g., a product code or other multi-dimensional code) are provided. In certain embodiments, joint optimization of coverage assignments, configuration assignments, rate assignments, and/or user data length assignments of an error-correction code is performed so as to achieve desired error-protection performance at minimized implementation complexity. In certain embodiments, coverage assignments of an error-correction code are optimized to achieve a desired performance level with minimized implementation complexity.

Abstract: Systems and methods for constructing concatenated codes for data storage channels, such as holographic storage channels, are provided. The concatenated codes include an outer BCH code and an inner iteratively decodable code, such as an LDPC code or turbo code. The correction power and coding rate of one or both of the codes may be programmable based on the channel characteristics and the desired SNR coding gain. The correction power and/or coding rate of the inner and/or outer code may also be dynamically adjusted in real-time to compensate for time-varying error conditions on the channel.

Abstract: A method includes applying an error-detecting code to first input data to generate first protected data and applying the error-detecting code to second input data to generate second protected data. The method also includes generating a first encoded codeword by encoding the first protected data using a first low density parity check (LDPC) code, and generating an output by performing a binary exclusive-or operation on the first protected data and the second protected data. The method further includes generating a second encoded codeword by encoding the output of the of the binary exclusive-or operation using a second LDPC code, and multiplexing data for transmission over a communications channel based on (i) the first encoded codeword and (ii) the second encoded codeword.

Abstract: Monitors, architectures, systems and methods for determining one or more quality characteristics of a storage channel. The monitor generally includes an iterative decoder configured to decode data from the storage channel and generate information relating to a quality metric of the storage channel and/or the iterative decoder, a memory configured to store a threshold value for the quality metric, and a comparator configured to compare the threshold value with a measured value of the quality metric. The monitor enables accurate determination of storage channel quality without use of conventional Reed-Solomon metrics.

Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. A 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

Abstract: An integrated circuit (IC) includes a decoding module configured to decode information units by performing T or less decoding iterations on each of the information units, where a maximum value of T is R, and where T is an integer greater than or equal to 1, and R is an integer greater than or equal to T. An iteration control module is configured to adjust a value of T based on a condition of the IC.

Abstract: This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders.

Abstract: The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes a single R memory component including R banks, a Q memory component including Q banks, a channel detector memory component to store channel extrinsic information associated with current and previous codewords, and an iterative decoder communicatively coupled with the single R memory component, the Q memory component, and the channel detector memory component. The apparatus can be configured to alternate among the R banks for storing R data associated with a current codeword. The apparatus can be configured to alternate among the Q banks for storing Q data associated with a current codeword.

Abstract: This disclosure relates generally to low power data decoding, and more particularly to low power data decoders for use under defects, erasures, and puncturing, with a low density parity check (LDPC) encoder. Systems and methods are disclosed for decoding a vector with punctured, detected defect and/or erased bits. Systems and methods are also disclosed for decoding a vector with undetected defects and/or unknown error patterns. Low power decoding may be performed in an LDPC decoder during the process of decoding an LDPC code in the case of defects, erasures, and puncturing. The low power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes, or the devices that make use of low power LDPC decoders.

Abstract: A defect detection and correction system includes a decoder module configured to decode data received from a data storage device and output the data and a plurality of confidence indicators associated with respective bits of the data. A digital defect detection module is configured to compare each of the confidence indicators in a window of W bits of the data to a confidence threshold, identify a number of bits in the window of W bits as defective based on the comparison, mark all of the bits in the window of W bits as defective if the number of bits is greater than a bit threshold, and generate a defect indicator identifying the window of W bits as defective.

Abstract: Systems and methods for decoding low density parity check (LDPC) codes are provided. An input message, representing a codeword encoded using a parity check matrix, is processed and data associated with each of the layers of the parity check matrix is computed. A first layer of the parity check matrix includes a first circulant configured to be updated using the data associated with a second layer of the parity check matrix. A second circulant in the first layer of the parity check matrix, configured to be updated using the data associated with the second layer of the parity check matrix, is identified. The first and second circulants are updated using the data associated with the first and second layers of the parity check matrix.

Abstract: Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput.