Abstract: An error correction system includes an iterative code that employs an interleaved component code and an embedded parity component code. On the transmission side, input signals received at an input node are encoded based on the interleaved code, which encodes an interleaved version of the input data to produce a first set of codewords. A portion of the first set of codewords is divided into a plurality of symbols which are encoded based on the embedded parity code. On the receiving side, received data are detected to produce detected information and soft outputs. The detected information is decoded based on the embedded parity code to obtain decoded information. The decoded information is used with other soft information by an interleaved decoder to generate reliability metrics for biasing a subsequent decoding iteration.

Abstract: Decoding data received includes decoding the received data using a first error correcting circuitry that decodes data in accordance with a first decoding process, terminating execution of the first decoding process used to correct the data before the first error correcting circuitry completes executing the first, decoding process and outputting partially decoded data, determining whether partially decoded data requires further decoding, and in response to determining whether partially decoded data requires further decoding, decoding the partially decoded data using a second error correcting circuitry that decodes data in accordance with a second decoding process. A system decodes data in accordance with the method.

Abstract: The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. In some implementations, an apparatus includes a memory module to communicate with an iterative code decoder. The memory module includes a single R memory component to store R data associated with a current codeword, and R data associated with a previous codeword. The memory module includes a Q memory component to store Q data associated with the current codeword, and Q data associated with the previous codeword. The memory module includes a channel detector memory component to store channel extrinsic information.

Abstract: Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix that corresponds to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check matrix is coupled to a high throughput LDPC decoder and a low throughput LDPC decoder, The super-parity-check matrix includes n parity check matrices, each including x rows corresponding to x check node processing elements and y columns corresponding to y bit node processing elements. Thus, the super-parity-check matrix comprises nx rows and ny columns. The numbers n, x, and y are selected so that ny codeword can be processed in single time unit by the high throughput decoder and y codeword bits can be processed in a single time unit by the low throughput decoder.

Abstract: Systems and methods are provided for decoding received codewords using an LDPC code. An LDPC post-processor is disclosed for performing post-processing when standard LDPC decoding fails due to a trapping set. The LDPC post-processor may direct the LDPC decoder to decode the received codeword again, but may change some of the inputs to the LDPC decoder so that the LDPC decoder does not fail in the same way. In one embodiment, the LDPC post-processor may modify the symbol positions in the received codeword that correspond to a particular unsatisfied check. In another embodiment, the LDPC post-processor may modify the messages in the decoder's iterative message algorithm that correspond to the symbol positions.

Abstract: An error rate sensitive error correction (ERSEC) system acting on product code is disclosed herein that improves error correction effectiveness by allocating error correction resources based on error susceptibility. The ERSEC system acts on vectors (bits or multiple-bit symbols) of a data matrix arranged from a data sequence. The ERSEC system obtains a signal-to-noise (SNR) profile that includes different SNR domains, assigns at least two vectors of the same dimension to different SNR domains, and allocates a level of error correction for the assigned vectors based on the SNR magnitudes of the assigned-to SNR domains.

Abstract: Systems and methods for jointly optimizing various parameters of an error-correction code (e.g., a product code or other multi-dimensional code) are provided. In certain embodiments, joint optimization of coverage assignments, configuration assignments, rate assignments, and/or user data length assignments of an error-correction code is performed so as to achieve desired error-protection performance at minimized implementation complexity. In certain embodiments, coverage assignments of an error-correction code are optimized to achieve a desired performance level with minimized implementation complexity.

Abstract: Systems and methods are provided for encoding data based on an LDPC code using various inversion mechanisms to obtain parity bits. In some embodiments, an LDPC encoder may compute parity bits using a speculative recursion and correction mechanism. In these embodiments, the LDPC encoder may initiate a recursion using at least one speculative value in place of the actual value for a parity component. The speculative values may then be corrected using a correction factor. In other embodiments, an LDPC encoder is provided that can perform a blockwise inversion mechanism. This mechanism may be used on LDPC codes with parity check matrices having a parity portion composed partially of a large triangular matrix. In still other embodiments, a generic LDPC encoder is provided. The generic LDPC encoder can implement a variety of different encoding techniques, such as different inversion mechanisms, and may be processor-based or finite state machine-based.

Abstract: Apparatus and methods are provided for calculating soft information in a multi-level modulation scheme using one or more nearest neighbors. The nearest neighbors correspond to signal points in a signal constellation set nearest to the value of a received signal. The nearest neighbors of a received signal can be found by using a second symbol-to-signal point mapping for the signal constellation set that is different from the mapping actually used by the signal modulator. The second symbol mapping can be used to simplify the discover of nearest neighbors. Once the nearest neighbors are found in the second symbol mapping, the nearest symbols can be translated back into the actual symbol mapping using, for example, table lookup. The nearest neighbors in the actual symbol mapping can then be used to compute soft information in the form of, for example, log-likelihood ratios (LLRs).

Abstract: Systems and methods for enhancing soft decoders and detectors on asymmetric channels are provided. The methods include acquiring log-likelihood ratios (LLRS) for error-correction code (ECC) encoded data symbols, selecting a quality measure function and a quality threshold based on the LLRs, applying the selected quality measure function to the LLRs to obtain quality measures, comparing the quality measures to the selected quality threshold, and updating the LLRs for selected ECC encoded data symbols based on the comparisons. The updating may occur by multiplying the LLRs for the selected ECC encoded data symbols by a selected scaling factor.

Abstract: In iterative decoding, a data recovery scheme corrects for corrupted or defective data by incorporating results from a previous decoding iteration. In one embodiment, a final multiplexer selects between the final detector output or a previous detector output based on the absence or presence of defective data. In another embodiment, the branch metrics for the defective data, which otherwise would be combined with a priori LLRs from an outer decoder of a prior stage, are ignored so that the a priori LLRs themselves are used alone. The two embodiments can be used together.

Abstract: Apparatus and methods are provided for calculating soft information in a multi-level modulation scheme using one or more nearest neighbors. The nearest neighbors correspond to signal points in a signal constellation set nearest to the value of a received signal. For the nearest neighbors of a received symbol of information, a detector can determine whether the nearest neighbors have a same bit value at a bit position of the symbol. When the bit values are the same at that bit position, soft information in the form a log-likelihood ratio can be computed based on the nearest neighbors and a predetermined scaling factor. The predetermined scaling factor can be optimized for system performance.

Abstract: A system includes a supernode generator module configured to generate supernodes. Each of the supernodes includes a plurality of symbol nodes. A supernode splitting module is configured to split each of the supernodes into derived symbols. The total number of edges of the derived symbols in each of the supernodes is equal to a predetermined number of edges of each of the supernodes.

Abstract: An error rate sensitive error correction (ERSEC) system that applies a level of error correction that is inversely related to susceptibility to error as indicated by a signal-to-noise ratio (SNR) profile of a channel. The SNR profile is estimated, detected or retrieved from an external source. The ERSEC system is used with a channel for which the SNRs vary spatially, temporally or both.

Abstract: This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders.

Abstract: Systems and methods for enhancing soft decoders and detectors on asymmetric channels are provided. The methods include acquiring log-likelihood ratios (LLRS) for error-correction code (ECC) encoded data symbols, selecting a quality measure function and a quality threshold based on the LLRs, applying the selected quality measure function to the LLRs to obtain quality measures, comparing the quality measures to the selected quality threshold, and updating the LLRs for selected ECC encoded data symbols based on the comparisons. The updating may occur by multiplying the LLRs for the selected ECC encoded data symbols by a selected scaling factor.

Abstract: A low-density parity-check (LDPC) decoder includes a plurality of bit node processing elements, and a plurality of check node processing elements. The LDPC decoder also includes a plurality of message passing memory blocks. A first routing matrix couples the plurality of bit node processing elements to the plurality of message passing memory blocks. A second routing matrix couples the plurality of check node processing elements to the plurality of message passing memory blocks. The first routing matrix and the second routing matrix enable each bit node to exchange LDPC decoding messages with an appropriate check node via a corresponding one of the message passing memory blocks.

Abstract: A device includes a supernode generator module, a supernode splitting module, and a control module. The supernode generator module generates S supernodes each comprising d symbol nodes, where S and d are integers greater than 1. The supernode splitting module splits each of the S supernodes into d derived symbols, wherein a total number of symbol edges of the d derived symbols is equal to a predetermined number of symbol edges of each of the S supernodes. The control module generates a quasi-cyclic irregular low density parity check (LDPC) code based on S*d derived symbols, wherein S equals the S supernodes and d equals the d derived symbols.

Abstract: An error rate sensitive error correction (ERSEC) system that applies a level of error correction that is inversely related to susceptibility to error as indicated by a signal-to-noise ratio (SNR) profile of a channel. The SNR profile is estimated, detected or retrieved from an external source. The ERSEC system can be used with any channel for which the SNRs vary spatially, temporally or both.

Abstract: Significant improvement in Raptor codes and punctured LDPC codes are obtainable by use of the invention. In both a transmission scheme for Raptor-encoded or LDPC-encoded information, a dynamic adjustment approach is employed. A fraction of a codeword or information frame is transmitted. A feedback signal is sent from the receiver to the transmitter indicating either 1) successful decoding, or 2) failure to decode and/or a feedback signal indicative of a statistical measure of transmission channel quality. If decoding fails, a further portion of the codeword or frame is sent. The intensity and/or size of the fraction is adjusted based on the feedback signal. In one embodiment, a specific range for probabilities employed in the encoding process for Raptor codes provides the ability to increase transmission throughput. Further it has been found that the advantageous Raptor codes are useful in noise conditions where even the improved punctured LDPC codes of the invention begin to degrade.