Abstract: Equipment for controlling a node in a wireless communication system can include a processor. The processor can identify scenarios under which at least one wireless communication system problem can occur, and metrics that characterize the scenarios. Based on the metrics the processor can generate a set of sub-problems, where a sub-problem of the set can correspond to a respective scenario. The processor can identify a set of algorithms for responding to respective sub-problems of the set of sub-problems to generate a module. The processor can provide control logic to determine which algorithm of the module to execute during operation of the wireless communication system based on detection of problems of an identified scenario. The processor can provide identification of a selected algorithm based on the determining. Communication circuitry can provide identification of the selected algorithm for execution within the wireless communication system.

Abstract: A device can include communication circuitry to communicate with radio units (RUs) over a fronthaul (FH) interface. The device can include a processor coupled to the communication circuitry to receive, over the communication interface, an indication of a number of multiple-input multiple-output (MIMO) layers to be scheduled, and information identifying the one or more RUs. The processor can assign a number of streams to the one or more RUs based on the number of MIMO layers. The processor can provide the assigning to the number of RUs over the FH interface.

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.

Abstract: Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.

Abstract: Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.

Abstract: An apparatus for use in an O-RAN base station includes processing circuitry. To configure the O-RAN base station for signal processing in an O-RAN network, the processing circuitry is to decode an SRS and a DMRS in a UL stream received from at least one UE. Channel estimation is performed based on the SRS to obtain a channel estimate matrix of channel estimates associated with reception of the UL stream. A noise covariance is generated using the DMRS. Beamforming weights are determined using the channel estimate matrix and the noise covariance. Beamforming is performed on UL data corresponding to the UL stream to generate beamformed data streams. The beamforming is based on applying the beamforming weights to the UL data.

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.

Abstract: This disclosure relates to apparatuses, systems, and methods for scheduling user equipment (UE) transmissions, and in particular for scheduling UE transmissions in a 5G New Radio system with a split architecture. The scheduler selects a beamforming algorithm for a UE group that includes a first UE and a second UE, where the beamforming algorithm is based on characteristics of the beamforming algorithm and/or the UE group. The scheduler determines an effective SINR for the UE group based on the beamforming algorithm and determines a summed proportion fair metric for the UE group based on the effective SINR for the UE group. The scheduler schedules a transmission for either the first UE or the UE group, based on a proportional fair metric for the first UE and the summed proportional fair metric for the UE group.

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.

Abstract: Systems, methods, and apparatus for workload optimized central processing units are disclosed herein. An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.

Abstract: Systems, apparatus, and methods to workload optimize hardware are disclosed herein. An example apparatus includes power control circuitry to determine an application ratio based on an instruction to be executed by one or more cores of a processor to execute a workload, and configure, before the execution of the workload, at least one of (i) the one or more cores of the processor based on the application ratio or (ii) uncore logic of the processor based on the application ratio, and execution circuitry to execute the workload with the at least one of the one or more cores or the uncore logic.

Abstract: An apparatus of a wireless device, such as a user equipment (UE), can include processing circuitry configured to perform one or more of the handover-related techniques disclosed herein. For example, when associated with moving with a plurality of mobile devices from coverage of a first cell to a second cell, the processing circuitry can detect the second cell. One or more parameters of the second cell can be measured. The one or more parameters can be communicated to one or more other mobile devices of the plurality of mobile devices.

Abstract: A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

Abstract: Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.

Abstract: An apparatus of a wireless device, such as a user equipment (UE), can include processing circuitry configured to perform one or more of the handover-related techniques disclosed herein. For example, when associated with moving with a plurality of mobile devices from coverage of a first cell to a second cell, the processing circuitry can detect the second cell. One or more parameters of the second cell can be measured. The one or more parameters can be communicated to one or more other mobile devices of the plurality of mobile devices.

Abstract: Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.

Abstract: An apparatus of a wireless device, such as a user equipment (UE), can include processing circuitry configured to perform one or more of the handover-related techniques disclosed herein. For example, when associated with moving with a plurality of mobile devices from coverage of a first cell to a second cell, the processing circuitry can detect the second cell. One or more parameters of the second cell can be measured. The one or more parameters can be communicated to one or more other mobile devices of the plurality of mobile devices.

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.

Abstract: An apparatus of a wireless device, such as a user equipment (UE), can include processing circuitry configured to perform one or more of the handover-related techniques disclosed herein. For example, when associated with moving with a plurality of mobile devices from coverage of a first cell to a second cell, the processing circuitry can detect the second cell. One or more parameters of the second cell can be measured. The one or more parameters can be communicated to one or more other mobile devices of the plurality of mobile devices.

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.