Patents by Inventor Neelam Chandwani
Neelam Chandwani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111531Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.Type: ApplicationFiled: September 15, 2023Publication date: April 4, 2024Inventors: Stephen T. PALERMO, Srihari MAKINENI, Shubha BOMMALINGAIAHNAPALLYA, Neelam CHANDWANI, Rany T. ELSAYED, Udayan MUKHERJEE, Lokpraveen MOSUR, Adwait PURANDARE
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Publication number: 20240056159Abstract: This disclosure relates to apparatuses, systems, and methods for scheduling user equipment (UE) transmissions, and in particular for scheduling UE transmissions in a 5G New Radio system with a split architecture. The scheduler selects a beamforming algorithm for a UE group that includes a first UE and a second UE, where the beamforming algorithm is based on characteristics of the beamforming algorithm and/or the UE group. The scheduler determines an effective SINR for the UE group based on the beamforming algorithm and determines a summed proportion fair metric for the UE group based on the effective SINR for the UE group. The scheduler schedules a transmission for either the first UE or the UE group, based on a proportional fair metric for the first UE and the summed proportional fair metric for the UE group.Type: ApplicationFiled: March 29, 2022Publication date: February 15, 2024Inventors: Thushara HEWAVITHANA, Ranjit CAVATUR, Neelam CHANDWANI, Ziyi LI, Bishwarup MONDAL
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Patent number: 11775298Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.Type: GrantFiled: July 20, 2020Date of Patent: October 3, 2023Assignee: Intel CorporationInventors: Stephen T. Palermo, Srihari Makineni, Shubha Bommalingaiahnapallya, Neelam Chandwani, Rany T. Elsayed, Udayan Mukherjee, Lokpraveen Mosur, Adwait Purandare
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Publication number: 20230217253Abstract: Systems, methods, and apparatus for workload optimized central processing units are disclosed herein. An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.Type: ApplicationFiled: March 26, 2021Publication date: July 6, 2023Inventors: Stephen Palermo, Srihari Makineni, Shubha Bommalingaiahnapallya, Rany ElSayed, Lokpraveen Mosur, Neelam Chandwani, Pinkesh Shah, Rajesh Gadiyar, Shrikant M. Shah, Uzair Qureshi
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Publication number: 20230205606Abstract: Systems, apparatus, and methods to workload optimize hardware are disclosed herein. An example apparatus includes power control circuitry to determine an application ratio based on an instruction to be executed by one or more cores of a processor to execute a workload, and configure, before the execution of the workload, at least one of (i) the one or more cores of the processor based on the application ratio or (ii) uncore logic of the processor based on the application ratio, and execution circuitry to execute the workload with the at least one of the one or more cores or the uncore logic.Type: ApplicationFiled: March 26, 2021Publication date: June 29, 2023Inventors: Stephen Palermo, Neelam Chandwani, Kshitij Doshi, Chetan Hiremath, Rajesh Gadiyar, Udayan Mukherjee, Daniel Towner, Valerie Parker, Shubha Bommalingaiahnapallya, Rany ElSayed
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Patent number: 11683728Abstract: An apparatus of a wireless device, such as a user equipment (UE), can include processing circuitry configured to perform one or more of the handover-related techniques disclosed herein. For example, when associated with moving with a plurality of mobile devices from coverage of a first cell to a second cell, the processing circuitry can detect the second cell. One or more parameters of the second cell can be measured. The one or more parameters can be communicated to one or more other mobile devices of the plurality of mobile devices.Type: GrantFiled: February 18, 2022Date of Patent: June 20, 2023Assignee: Intel CorporationInventors: Mustafa Akdeniz, Dave A. Cavalcanti, Thorsten Clevorn, Brent Elliott, Jeffrey R. Foerster, Mikhail T. Galeev, Benjamin Grewell, Nageen Himayat, Shadi Iskander, Udayan Mukherjee, Harry G. Skinner, Susruth Sudhakaran, Candy Yiu, Chetan Hiremath, Neelam Chandwani, Jesus Martinez
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Publication number: 20230187407Abstract: A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.Type: ApplicationFiled: December 10, 2021Publication date: June 15, 2023Applicant: Intel CorporationInventors: Carleton L. Molnar, Adel A. Elsherbini, Tanay Karnik, Shawna M. Liff, Robert J. Munoz, Julien Sebot, Johanna M. Swan, Nevine Nassif, Gerald S. Pasdast, Krishna Bharath, Neelam Chandwani, Dmitri E. Nikonov
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Publication number: 20230109635Abstract: Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.Type: ApplicationFiled: March 26, 2021Publication date: April 6, 2023Inventors: Stephen T. Palermo, Chetan Hiremath, Rajesh Gadiyar, Jason K. Smith, Valerie J. Parker, Udayan Mukherjee, Neelam Chandwani, Francesc Guim Bernat, Ned M. Smith
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Publication number: 20220312277Abstract: An apparatus of a wireless device, such as a user equipment (UE), can include processing circuitry configured to perform one or more of the handover-related techniques disclosed herein. For example, when associated with moving with a plurality of mobile devices from coverage of a first cell to a second cell, the processing circuitry can detect the second cell. One or more parameters of the second cell can be measured. The one or more parameters can be communicated to one or more other mobile devices of the plurality of mobile devices.Type: ApplicationFiled: February 18, 2022Publication date: September 29, 2022Inventors: Mustafa Akdeniz, Dave A. Cavalcanti, Thorsten Clevorn, Brent Elliott, Jeffrey R. Foerster, Mikhail T. Galeev, Benjamin Grewell, Nageen Himayat, Shadi Iskander, Udayan Mukherjee, Harry G. Skinner, Susruth Sudhakaran, Candy Yiu, Chetan Hiremath, Neelam Chandwani, Jesus Martinez
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Publication number: 20220222194Abstract: Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.Type: ApplicationFiled: April 1, 2022Publication date: July 14, 2022Inventors: Neelam CHANDWANI, Shridhar BENDI, Rajesh VIVEKANANDHAM, Rahul PAL, Eric J. DAHLEN, Antonio J. HASBUN MARIN, Chung-Chi WANG, Qian LI, Hosein NIKOPOUR, Sravanthi KOTA VENKATA, Rajesh POORNACHANDRAN, Udayan MUKHERJEE
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Patent number: 11290923Abstract: An apparatus of a wireless device, such as a user equipment (UE), can include processing circuitry configured to perform one or more of the handover-related techniques disclosed herein. For example, when associated with moving with a plurality of mobile devices from coverage of a first cell to a second cell, the processing circuitry can detect the second cell. One or more parameters of the second cell can be measured. The one or more parameters can be communicated to one or more other mobile devices of the plurality of mobile devices.Type: GrantFiled: June 28, 2018Date of Patent: March 29, 2022Assignee: Intel CorporationInventors: Mustafa Akdeniz, Dave A. Cavalcanti, Thorsten Clevorn, Brent Elliott, Jeffrey R. Foerster, Mikhail T. Galeev, Benjamin Grewell, Nageen Himayat, Shadi Iskander, Udayan Mukherjee, Harry G. Skinner, Susruth Sudhakaran, Candy Yiu, Chetan Hiremath, Neelam Chandwani, Jesus Martinez
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Publication number: 20210334101Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.Type: ApplicationFiled: July 20, 2020Publication date: October 28, 2021Inventors: Stephen T. Palermo, Srihari Makineni, Shubha Bommalingaiahnapallya, Neelam Chandwani, Rany T. Elsayed, Udayan Mukherjee, Lokpraveen Mosur, Adwait Purandare
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Publication number: 20200252838Abstract: An apparatus of a wireless device, such as a user equipment (UE), can include processing circuitry configured to perform one or more of the handover-related techniques disclosed herein. For example, when associated with moving with a plurality of mobile devices from coverage of a first cell to a second cell, the processing circuitry can detect the second cell. One or more parameters of the second cell can be measured. The one or more parameters can be communicated to one or more other mobile devices of the plurality of mobile devices.Type: ApplicationFiled: June 28, 2018Publication date: August 6, 2020Inventors: Mustafa Akdeniz, Dave A. Cavalcanti, Thorsten Clevorn, Brent Elliott, Jeffery R. Foerster, Mikhail T. Galeev, Benjamin Grewell, Nageen Himayat, Shadi Iskander, Udayan Mukherjee, Harry G. Skinner, Susruth Sudhakaran, Candy Yiu, Chetan Hiremath, Neelam Chandwani, Jesus Martinez
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Patent number: 10514931Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.Type: GrantFiled: July 31, 2018Date of Patent: December 24, 2019Assignee: Intel CorporationInventors: Mohan Kumar, Sarathy Jayakumar, Neelam Chandwani
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Publication number: 20190065211Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.Type: ApplicationFiled: July 31, 2018Publication date: February 28, 2019Applicant: Intel CorporationInventors: Mohan Kumar, Sarathy Jayakumar, Neelam Chandwani
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Patent number: 10078522Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.Type: GrantFiled: November 21, 2012Date of Patent: September 18, 2018Assignee: Intel CorporationInventors: Mohan Kumar, Sarathy Jayakumar, Neelam Chandwani
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Patent number: 10007528Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.Type: GrantFiled: November 21, 2012Date of Patent: June 26, 2018Assignee: Intel CorporationInventors: Guy M. Therien, Paul Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann, Mohan Kumar, Sarathy Jayakumar, Jose Andy Vargas, Neelam Chandwani, Michael A. Rothman, Robert Gough, Mark Doran
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Patent number: 9104409Abstract: A method to reduce memory power consumption for a computing platform includes inspecting an operating parameter associated with a resource of the computing platform that is updated by the resource of the computing platform during runtime of the computing platform. Memory power utilization is then predicted for the computing platform during the runtime of the computing platform based at least in part on the operating parameter. A current power state of at least one memory module resident on the computing platform is transitioned to one of a plurality of power states based on the predicting of the memory power utilization.Type: GrantFiled: April 1, 2010Date of Patent: August 11, 2015Assignee: Intel CorporationInventors: Rakesh Dodeja, Neelam Chandwani, Chetan Hiremath, Udayan Mukherjee, Anthony Ambrose
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Publication number: 20140059368Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.Type: ApplicationFiled: November 21, 2012Publication date: February 27, 2014Inventors: Neelam Chandwani, Mohan Kumar, Sarathy Jayakumar
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Publication number: 20130151569Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.Type: ApplicationFiled: November 21, 2012Publication date: June 13, 2013Inventors: Guy Therien, Paul Diefenbaugh, Anil Aggarwal, Andrew Henroid, Jeremy Shrall, Efraim Rotem, Krishnakanth Sistla, Eliezer Weissmann, Mohan Kumar, Sarathy Jayakumar, Jose Andy Vargas, Neelam Chandwani, Michael A. Rothman, Robert Gough, Mark Doran