Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Abstract: A method to reduce memory power consumption for a computing platform includes inspecting an operating parameter associated with a resource of the computing platform that is updated by the resource of the computing platform during runtime of the computing platform. Memory power utilization is then predicted for the computing platform during the runtime of the computing platform based at least in part on the operating parameter. A current power state of at least one memory module resident on the computing platform is transitioned to one of a plurality of power states based on the predicting of the memory power utilization.

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

Abstract: Described herein are a method and an apparatus for reducing power consumption of memories by monitoring the power states of the memories via an operating system. The method comprises reading counter values corresponding to power states of each memory of a plurality memories; computing a power state usage corresponding to the power states of each memory of the plurality, the computing based on the counter values; determining whether the power state usage exceeds a predetermined threshold usage; and adjusting current and future usage of each memory of the plurality in response to determining that the power state usage exceeds the predetermined threshold usage.

Abstract: Described herein are a method and an apparatus for reducing power consumption of memories by monitoring the power states of the memories via an operating system. The method comprises reading counter values corresponding to power states of each memory of a plurality memories; computing a power state usage corresponding to the power states of each memory of the plurality, the computing based on the counter values; determining whether the power state usage exceeds a predetermined threshold usage; and adjusting current and future usage of each memory of the plurality in response to determining that the power state usage exceeds the predetermined threshold usage.

Abstract: Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel.

Abstract: A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.

Abstract: A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.

Abstract: A method for managing a system includes monitoring a plurality of applications running in the system for errors. A prediction is made as to whether errors detected would result in a failure. Fault recovery is initiated in response to a failure prediction. According to one aspect of the present invention, monitoring the plurality of applications includes reading error recorders associated with error occurrence. Other embodiments are described and claimed.

Abstract: Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel.

Abstract: A hardware management module is enabled to perform hardware management for a modular platform system that includes a plurality of modular platform shelves coupled via one or more communication links in a network. Hardware management to include monitoring board interfaces resident on one or more backplanes within the plurality of modular platform shelves, detecting when a board is received and coupled to a board interface and performing one or more hardware management functions to include obtaining field replaceable unit information from the detected board.

Abstract: A fault module supports detection, analysis, and/or logging of various faults in a processor system. In one embodiment, the system is provided on a multi-core, single die device.

Abstract: Faults are monitored with information from agents for a plurality of sensors located on a plurality of circuit boards. A policy containing a error event thresholds against which the stored sensor information can be compared. Actions can be initiated by a fault module when one or more of the error event thresholds is exceeded.

Abstract: A method is to include implementing at least one statistical prediction model to predict memory power utilization and reduce power consumption for a computing platform. The implementation includes determining a configuration parameter for the computing platform, monitoring an operating parameter for the computing platform and predicting memory power utilization for the computing platform based on the determined configuration parameter and the monitored operating parameter. The method is to also include transitioning at least one memory module resident on the computing platform to one of a plurality of power states based at least in part on memory power utilization predicted via the implementation of the at least one statistical prediction model.

Abstract: A modeling module is disclosed that couples to a modular platform chassis. The modeling module includes a resident management controller to implement a test to model a component layout for a module to be received and coupled to the modular platform chassis. The test includes an operating thermal load for a component resident on the module at a given location. The module has a dimensional length and width that is similar to that of the modeling module. The modeling module also includes a thermal load device that is responsive to the management controller. The thermal load device is to implement at least a portion of the test by simulating the operating thermal load for the component resident on the module at the given location.

Abstract: Faults are monitored with information from agents for a plurality of sensors located on a plurality of circuit boards. A policy containing a error event thresholds against which the stored sensor information can be compared. Actions can be initiated by a fault module when one or more of the error event thresholds is exceeded.

Abstract: A fault module supports detection, analysis, and/or logging of various faults in a processor system. In one embodiment, the system is provided on a multi-core, single die device.