Patents by Inventor NEELAM

NEELAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230207492
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a via opening is formed through a thickness of the substrate, and a first layer is over sidewalls of the via opening. In an embodiment, the first layer comprises a magnetic material. In an embodiment, a second layer is over the first layer, where the second layer is an insulator. In an embodiment, a third layer fills the via opening, where the third layer is a conductor.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Aleksandar ALEKSOV, Georgios C. DOGIAMIS, Neelam PRABHU GAUNKAR, Telesphor KAMGAING, Veronica STRONG, Brandon RAWLINGS, Robert MONGRAIN, Beomseok CHOI
  • Publication number: 20230207408
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a core. In an embodiment, the core comprises glass. In an embodiment, a blind via is provided into the core. In an embodiment, a plate spans across the blind via.
    Type: Application
    Filed: December 24, 2021
    Publication date: June 29, 2023
    Inventors: Georgios C. DOGIAMIS, Aleksandar ALEKSOV, Telesphor KAMGAING, Neelam PRABHU GAUNKAR, Brandon RAWLINGS, Veronica STRONG
  • Publication number: 20230207407
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a via opening is formed through the core. In an embodiment, the via opening has an aspect ratio (depth:width) that is approximately 5:1 or greater. In an embodiment, the electronic package further comprises a via in the via opening, where the via opening is fully filled.
    Type: Application
    Filed: December 24, 2021
    Publication date: June 29, 2023
    Inventors: Georgios C. DOGIAMIS, Telesphor KAMGAING, Brandon RAWLINGS, Neelam PRABHU GAUNKAR, Veronica STRONG, Aleksandar ALEKSOV
  • Publication number: 20230197592
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a core with a first surface and a second surface, where the core comprises glass. In an embodiment, a first buildup layer is over the first surface of the core, and a second buildup layer is under the second surface of the core. In an embodiment, the electronic package further comprises a via through the core between the first surface of the core and the second surface of the core, and a plane into the first surface of the core, where a width of the plane is greater than a width of the via.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Inventors: Telesphor KAMGAING, Brandon RAWLINGS, Aleksandar ALEKSOV, Andrew P. COLLINS, Georgios C. DOGIAMIS, Veronica STRONG, Neelam PRABHU GAUNKAR
  • Publication number: 20230197541
    Abstract: Embodiments disclosed herein include an electronic package that comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass. In an embodiment, the electronic package further comprises an opening through the substrate from the first surface to the second surface, where the opening comprises a first end proximate to the first surface of the substrate, a second end proximate to the second surface of the substrate, and a middle region between the first end and the second end. In an embodiment, the middle region has a discontinuous slope at junctions with the first end and the second end.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Veronica STRONG, Telesphor KAMGAING, Aleksandar ALEKSOV, Georgios C. DOGIAMIS, Brandon RAWLINGS, Neelam PRABHU GAUNKAR
  • Publication number: 20230194607
    Abstract: A scan chain architecture with lowered power consumption comprises a multiplexer selecting between a functional input and a test input. The output of the multiplexer is coupled to a low threshold voltage latch and, in test mode, to a standard threshold voltage latch. The low threshold voltage latch and standard threshold voltage latch are configured to store data when a clock input falls, using a master latch functional clock M_F_CLK, master latch test clock M_T_CLK, slave latch functional clock S_F_CLK, and slave latch test clock S_T_CLK. The slave latch has lower power consumption than the master latch.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Applicant: Ceremorphic, Inc.
    Inventors: Shakti SINGH, Neelam SURANA, Robert F. Wiser
  • Publication number: 20230197121
    Abstract: A memory performing logic functions has two single transistor static ram memory (STSRAM) with drain, source, and gate terminal which can be written, read, and when read, generates an output current. The STSRAMs have drain and source connected in parallel, and when read, generate a current provided to a current comparator amplifier (CCA) which is compared to a reference current Iref to generate an output which is at least one of a logical AND, logical NAND, logical OR, logical NOR, or logical exclusive OR (XOR).
    Type: Application
    Filed: December 19, 2021
    Publication date: June 22, 2023
    Applicant: Ceremorphic, Inc.
    Inventors: Neelam SURANA, Robert F. WISER
  • Publication number: 20230197646
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a trace embedded in the substrate, where a width of the trace is less than a height of the trace. In an embodiment, the electronic package further comprises a first layer on the first surface of the substrate, where the first layer is a dielectric buildup film, and a second layer on the second surface of the substrate, where the second layer is the dielectric buildup film.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Aleksandar ALEKSOV, Telesphor KAMGAING, Georgios C. DOGIAMIS, Neelam PRABHU GAUNKAR, Veronica STRONG, Brandon RAWLINGS, Andrew P. COLLINS, Arghya SAIN, Sivaseetharaman PANDI
  • Publication number: 20230197620
    Abstract: Methods, systems, apparatus, and articles of manufacture are disclosed for integrated circuit package substrates with high aspect ratio through glass vias. An example microelectronic package including a glass substrate including a via, the via including a high aspect ratio. The example microelectronic package further including a seed layer extending substantially evenly along an inner wall of the via.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Veronica Strong, Aleksandar Aleksov, Georgios Dogiamis, Telesphor Kamgaing, Neelam Prabhu Gaunkar, Brandon Rawlings
  • Publication number: 20230197146
    Abstract: A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.
    Type: Application
    Filed: December 19, 2021
    Publication date: June 22, 2023
    Applicant: Ceremorphic, Inc.
    Inventors: Robert F. WISER, Neelam SURANA
  • Publication number: 20230198058
    Abstract: Embedded batteries within glass cores are disclosed. Example apparatus include a glass core layer having opposing first and second surfaces, the glass core layer including a cavity extending from the first surface toward the second surface, and a battery including a first conductive material positioned in the cavity, a second conductive material positioned in the cavity, and an electrolyte to separate the first conductive material from the second conductive material.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Inventors: Veronica Strong, Telesphor Kamgaing, Neelam Prabhu Gaunkar, Georgios Dogiamis, Aleksandar Aleksov, Brandon Rawlings
  • Patent number: 11683728
    Abstract: An apparatus of a wireless device, such as a user equipment (UE), can include processing circuitry configured to perform one or more of the handover-related techniques disclosed herein. For example, when associated with moving with a plurality of mobile devices from coverage of a first cell to a second cell, the processing circuitry can detect the second cell. One or more parameters of the second cell can be measured. The one or more parameters can be communicated to one or more other mobile devices of the plurality of mobile devices.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: June 20, 2023
    Assignee: Intel Corporation
    Inventors: Mustafa Akdeniz, Dave A. Cavalcanti, Thorsten Clevorn, Brent Elliott, Jeffrey R. Foerster, Mikhail T. Galeev, Benjamin Grewell, Nageen Himayat, Shadi Iskander, Udayan Mukherjee, Harry G. Skinner, Susruth Sudhakaran, Candy Yiu, Chetan Hiremath, Neelam Chandwani, Jesus Martinez
  • Publication number: 20230187407
    Abstract: A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 15, 2023
    Applicant: Intel Corporation
    Inventors: Carleton L. Molnar, Adel A. Elsherbini, Tanay Karnik, Shawna M. Liff, Robert J. Munoz, Julien Sebot, Johanna M. Swan, Nevine Nassif, Gerald S. Pasdast, Krishna Bharath, Neelam Chandwani, Dmitri E. Nikonov
  • Patent number: 11675215
    Abstract: This disclosure describes, in part, eyeglass systems configured to automatically adjust an optical-power value, or optical power, of lenses of the eyeglass system based on the distance between eyes of a user wearing the eyeglass system and an object that the user is looking at. In some instances, the eyeglass system may determine a degree-of-convergence (DoC) or convergence angle between the left eye and the right eye of the user to determine the distance between the eyes of the user and the object the user is viewing. Further, the eyeglass system may include a power source and lenses that change their optical-power value based on different voltage or current values provided to the lenses by the power source.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: June 13, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Neelam Rani, Sakthi Ramanathan Sivaraman
  • Publication number: 20230177076
    Abstract: Methods, systems, and computer program products for extracting query-related temporal information from unstructured text documents are provided herein. A computer-implemented method includes obtaining at least one user query comprising one or more temporal components; converting at least a portion of the at least one user query into one or more logic form representations; mapping at least a portion of the one or more logic form representations to one or more portions of at least one source of unstructured text data; extracting temporal information, specific to the at least one user query, from one or more portions of the at least one source of unstructured text data based on the mapping; generating at least one response to the at least one user query based on the extracted temporal information; and performing one or more automated actions based on the at least one generated response.
    Type: Application
    Filed: December 6, 2021
    Publication date: June 8, 2023
    Inventors: Udit Sharma, Hima Prasad Karanam, Shajith Ikbal Mohamed, Sumit Neelam, Santosh Srivastava, L. Venkata Subramaniam
  • Publication number: 20230169115
    Abstract: Methods, systems, and computer program products for partitioning and parallel loading of property graphs with constraints are provided herein. A computer-implemented method includes obtaining graph-related input data and corresponding constraint data, wherein the graph-related input data and corresponding constraint data are at least one of user-defined and input data model-based; generating at least one in-memory graph based at least in part on processing at least a portion of the obtained graph-related input data; partitioning the at least one in-memory graph into two or more sub-graphs by processing the at least one in-memory graph using one or more polynomial time partition algorithms; and generating at least one property graph by allocating, at least a portion of the two or more partitioned sub-graphs which satisfy the obtained constraint data, to two or more threads that run in parallel.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Inventors: Sumit Neelam, Hima Prasad Karanam, Udit Sharma, Shajith Ikbal Mohamed, Santosh Srivastava, L. Venkata Subramaniam
  • Patent number: 11645056
    Abstract: Capturing dependencies between variables using a variable agnostic object is disclosed. A system is configured to obtain an indication of a first dependency of a first variable to a second variable via a programming interface and depict the first dependency, the first variable, and the second variable in a first instance of a variable agnostic object in a source code. The system is also configured to obtain an indication of a second dependency of a third variable to a fourth variable via the programming interface and depict the second dependency, the third variable, and the fourth variable in a second instance of the variable agnostic object in the source code. The system is also configured to compile the source code to generate a computer-executable program capturing the first dependency and the second dependency based on the first instance and the second instance of the variable agnostic object.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: May 9, 2023
    Assignee: Intuit Inc.
    Inventors: Samarinder Singh Thind, Rajat Khare, Neelam Singh, Suresh Krishna Devanathan, Deepak Radhakrishna
  • Publication number: 20230128674
    Abstract: This disclosure provides recombinant DNA constructs and transgenic plants having enhanced traits such as increased yield, increased nitrogen use efficiency, and enhanced drought tolerance or water use efficiency. Transgenic plants may include field crops as well as plant propagules, plant parts and progeny of such transgenic plants. Methods of making and using such transgenic plants are also provided. This disclosure also provides methods of producing seed from such transgenic plants, growing such seed, and selecting progeny plants with enhanced traits. Also disclosed are transgenic plants with altered phenotypes which are useful for screening and selecting transgenic events for the desired enhanced trait.
    Type: Application
    Filed: August 4, 2022
    Publication date: April 27, 2023
    Inventors: Thomas R. Adams, Molian Deng, Charles Dietrich, Stephen M. Duff, Karen K. Gabbert, Angel D. Hoelscher, Balasulojini Karunanandaa, Linda L. Lutfiyya, Michael H. Malone, Anil Neelam, Thomas L. Slewinski, Jindong Sun, Tyamagondlu V. Venkatesh, Jianmin Zhao
  • Publication number: 20230110884
    Abstract: The present disclosure provides compositions and methods for altering gibberellin (GA) content in corn or other cereal plants. Methods and compositions are also provided for altering the expression of genes related to gibberellin biosynthesis through suppression, mutagenesis and/or editing of specific subtypes of GA20 or GA3 oxidase genes. Modified plant cells and plants having a suppression element or mutation reducing the expression or activity of a GA oxidase gene are further provided comprising reduced gibberellin levels and improved characteristics, such as reduced plant height and increased lodging resistance, but without off-types.
    Type: Application
    Filed: June 22, 2022
    Publication date: April 13, 2023
    Applicant: MONSANTO TECHNOLOGY LLC
    Inventors: Edwards Allen, Jayanand BODDU, Charles R. DIETRICH, Alexander GOLDSHMIDT, Miya HOWELL, Kevin R. KOSOLA, Silvalinganna MANJUNATH, Anil NEELAM, Linda RYMARQUIS, Thomas L. SLEWINSKI, Tyamagondlu V. VENKATESH, Huai WANG
  • Publication number: 20230109635
    Abstract: Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.
    Type: Application
    Filed: March 26, 2021
    Publication date: April 6, 2023
    Inventors: Stephen T. Palermo, Chetan Hiremath, Rajesh Gadiyar, Jason K. Smith, Valerie J. Parker, Udayan Mukherjee, Neelam Chandwani, Francesc Guim Bernat, Ned M. Smith