Patents by Inventor Neil Burgess

Neil Burgess has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180307488
    Abstract: An apparatus has processing circuitry comprising an L×M multiplier array. An instruction decoder associated with the processing circuitry supports a multiply-and-accumulate-product (MAP) instruction for generating at least one result element corresponding to a sum of respective E×F products of E-bit and F-bit portions of J-bit and K-bit operands respectively, where 1<E<J?L and 1<F<K?M. In response to the MAP instruction, the instruction decoder controls the processing circuitry to rearrange F-bit portions of the second K-bit operand to form a transformed K-bit operand, and to control the L×M multiplier array in dependence on the first J-bit operand and the transformed K-bit operand to add the respective E×F products using a subset of the adders used for accumulating partial products for a conventional multiplication.
    Type: Application
    Filed: April 24, 2017
    Publication date: October 25, 2018
    Inventors: Neil BURGESS, David Raymond LUTZ, Javier Diaz BRUGUERA
  • Publication number: 20180307489
    Abstract: An apparatus and method are provided for performing multiply-and-accumulate-products (MAP) operations. The apparatus has processing circuitry for performing data processing, the processing circuitry including an adder array having a plurality of adders for accumulating partial products produced from input operands. An instruction decoder is provided that is responsive to a MAP instruction specifying a first J-bit operand and a second K-bit operand, to control the processing circuitry to enable performance of a number of MAP operations, where the number is dependent on a parameter. For each performed MAP operation, the processing circuitry is arranged to generate a corresponding result element representing a sum of respective E×F products of E-bit portions within an X-bit segment of the first operand with F-bit portions within a Y-bit segment of the second operand, where E<X?J and F<Y?K.
    Type: Application
    Filed: January 2, 2018
    Publication date: October 25, 2018
    Inventors: Michael Alexander KENNEDY, Neil BURGESS
  • Publication number: 20180217815
    Abstract: An apparatus and method are provided for processing input operand values. The apparatus has a set of vector data storage elements, each vector data storage element providing a plurality of sections for storing data values. A plurality of lanes are considered to be provided within the set of storage elements, where each lane comprises a corresponding section from each vector data storage element. Processing circuitry is arranged to perform an arithmetic operation on an input operand value comprising a plurality of portions, by performing an independent arithmetic operation on each of the plurality of portions, in order to produce a result value comprising a plurality of result portions. Storage circuitry is arranged to store the result value within a selected lane of the plurality of lanes, such that each result portion is stored in a different vector data storage element within the corresponding section for the selected lane.
    Type: Application
    Filed: December 6, 2017
    Publication date: August 2, 2018
    Inventors: Christopher Neal HINDS, Neil BURGESS, David Raymond LUTZ
  • Publication number: 20180157464
    Abstract: An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions in order to generate control signals to control the arithmetic operations performed by the execution circuitry. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding such a convert and accumulate instruction within the sequence of instructions to generate one or more control signals to control the execution circuitry. In particular, the execution circuitry is responsive to such control signals to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand.
    Type: Application
    Filed: December 6, 2016
    Publication date: June 7, 2018
    Inventors: David Raymond LUTZ, Neil BURGESS, Christopher Neal HINDS, Andreas Due ENGH-HALSTVEDT
  • Patent number: 9928031
    Abstract: Processing circuitry is provided to perform an overlap propagating operation on a first data value to generate a second data value, the first and second data values having a redundant representation representing a P-bit numeric value using an M-bit data value comprising a plurality of N-bit portions, where M>P>N. In the redundant representation, each N-bit portion other than a most significant N-bit portion includes a plurality of overlap bits having a same significance as a plurality of least significant bits of a following N-bit portion. Each N-bit portion of the second data value other than a least significant N-bit portion is generated by adding non-overlap bits of a corresponding N-bit portion of the first data value to the overlap bits of a preceding N-bit portion of the first data value. This provides a faster technique for reducing the chance of overflow during addition of the redundantly represented M-bit value.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: March 27, 2018
    Assignee: ARM LIMITED
    Inventors: Neil Burgess, David Raymond Lutz, Christopher Neal Hinds
  • Patent number: 9916130
    Abstract: An apparatus comprises processing circuitry for performing, in response to a vector instruction, a plurality of lanes of processing or respective data elements with at least one operand vector to generate corresponding result data elements of a result vector. The processing circuitry may support performing at least two of the lanes of processing with different rounding modes for generating rounding values for the corresponding result data elements of the result vector. This allows two or more calculations with different rounding modes to be executed in response to a single instruction, to improve performance.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: March 13, 2018
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess
  • Publication number: 20180046459
    Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising an ordered plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the vector positions; predicate generation circuitry to apply a processing operation to generate an ordered set of predicate indicators, each associated with a respective one of the vector positions, the ordered set of predicate indicators being associated with an ordered set of active indicators each having an active or an inactive state; and a detector to detect a status flag indicative of whether a predicate indicator at a position, in the ordered set of predicate indicators, corresponding to the position of an outermost active indicator having the active state, has a given state; in which the detector comprises: first and second circuitry to combine the ordered set of predic
    Type: Application
    Filed: August 15, 2016
    Publication date: February 15, 2018
    Inventors: Neil BURGESS, Lee Evan EISEN, Gary Alan GORMAN, Daniel ARULRAJ
  • Publication number: 20180046460
    Abstract: Data processing apparatus comprises: processing circuitry to selectively apply vector processing operations to one or more data items of one or more data vectors each comprising a plurality of data items at respective vector positions in the data vector, according to the state of respective predicate indicators associated with the vector positions; a predicate store; and predicate generation circuitry to apply a processing operation to generate a set of predicate indicators, each associated with a respective one of the vector positions, to generate a count value indicative of the number of predicate indicators in the set having a given state, and to store the generated set of predicate indicators and the count value in the predicate store.
    Type: Application
    Filed: August 15, 2016
    Publication date: February 15, 2018
    Inventors: Gary Alan GORMAN, Lee Evan EISEN, Neil BURGESS, Daniel ARULRAJ
  • Patent number: 9817661
    Abstract: A data processing system supports execution of program instructions having a rounding position input operand so as to generate control signals for controlling processing circuitry to process a floating point input operand with a significand value to generate an output result which depends upon a value from rounding the floating point input operand using a variable rounding point within the significand of the floating point input operand as specified by the rounding position input operand. In this way, processing operations having as inputs floating point operands and anchored number operands may be facilitated.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: November 14, 2017
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Christopher Neal Hinds, Neil Burgess
  • Publication number: 20170293467
    Abstract: A data processing system 2 includes instruction decoder circuitry 12 responsive to a conversion instruction FCVTJS to convert a double precision floating point number into a 32-bit integer number. Right shifting circuitry 28 performs a right shift upon at least part of the input number and left shifting circuitry 32 performs a left shift of at least part of the input number. Selection circuitry 38 serves to select one of the right shifted number and the left shifted number as a selected shifted number which forms at least part of the output number which is generated.
    Type: Application
    Filed: April 8, 2016
    Publication date: October 12, 2017
    Inventors: David Raymond LUTZ, Neil BURGESS, Kelvin Domnic GOVEAS
  • Patent number: 9785407
    Abstract: A processing apparatus has combined divide-square root circuitry for performing a radix-N SRT divide algorithm and a radix-N SRT square root algorithm, where N is an integer power-of-2. The combined circuitry has shared remainder updating circuitry which performs remainder updates for a greater number of iterations per cycle for the SRT divide algorithm than for the SRT square root algorithm. This allows reduced circuit area while avoiding the SRT square root algorithm compromising the performance of the SRT divide algorithm.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: October 10, 2017
    Assignee: ARM Limited
    Inventors: Neil Burgess, David Raymond Lutz
  • Patent number: 9778906
    Abstract: An apparatus comprises processing circuitry to perform a conversion operation to convert a floating-point value to a vector comprising a plurality of data elements representing respective bit significance portions of a binary value corresponding to the floating-point value.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: October 3, 2017
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess, Christopher Neal Hinds
  • Patent number: 9766857
    Abstract: An apparatus includes processing circuitry to perform one or more arithmetic operations for generating a result value based on at least one operand. For at least one arithmetic operation, the processing circuitry is responsive to programmable significance data indicative of a target significance for the result value, to generate the result value having the target significance. For example, this allows programmers to set a significance boundary for the arithmetic operation so that it is not necessary for the processing circuitry to calculate bit values having a significance outside the specified boundary, enabling a performance improvement.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: September 19, 2017
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess, Christopher Neal Hinds
  • Patent number: 9766858
    Abstract: A data processing system supports vector operands with components representing different bit significance portions of an integer number. Processing circuitry performs a processing operation specified by a program instruction in dependence upon a number of components comprising the vector as specified by metadata for the vector.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: September 19, 2017
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess, Christopher Neal Hinds
  • Patent number: 9733899
    Abstract: Processing circuitry performs a plurality of lanes of processing on respective data elements of at least one operand vector to generate corresponding result data elements of a result vector. The processing circuitry identifies lane position information for each lane of processing, the lane position information for a given lane identifying a relative position of the corresponding result data element to be generated by the given lane within a corresponding result data value spanning one or more result data elements of the result vector. The processing circuitry is configured to perform each lane of processing in dependence on the lane position information identified for that lane. This enables generation of results which are wider or narrower than the vector size supported in hardware.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: August 15, 2017
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess, Christopher Neal Hinds
  • Patent number: 9720646
    Abstract: A redundant representation is provided where an M-bit value represents a P-bit numeric value using a plurality of N-bit portions, where M>P>N. An anchor value identifies the significance of bits of each N-bit, and within a group of at least two adjacent N-bit portions, two or more overlap bits of a lower N-bit portion of the group have a same significance as two or more least significant bits of at least one upper N-bit portion of the group. A plurality of operation circuit units can perform a plurality of independent N-bit operation in parallel, each N-bit operation comprising computing a function of corresponding N-bit portions of at least two M-bit operand values having the redundant representation to generate a corresponding N-bit portion of an M-bit result value having the redundant representation. This enables fast associative processing of relatively long M-bit values in the time taken for performing an N-bit operation.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: August 1, 2017
    Assignee: ARM Limited
    Inventors: Neil Burgess, David Raymond Lutz, Christopher Neal Hinds
  • Patent number: 9710229
    Abstract: A data processing apparatus has a processing circuitry for performing a floating-point square root operation on a radicand value R to generate a result value. The processing circuitry has first square root processing circuitry for processing radicand values R which are not an exact power of two and second square root processing circuitry for processing radicand values which are an exact power of 2. Power-of-two detection circuitry detects whether the radicand value is an exact power of two and selects the output of the first or second square root processing circuitry as appropriate. This allows the result to be generated in fewer processing cycles when the radicand is a power of 2.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: July 18, 2017
    Assignee: ARM Limited
    Inventors: Neil Burgess, David Raymond Lutz
  • Patent number: 9703531
    Abstract: A method is provided for multiplying a first operand comprising at least two X-bit portions and a second operand comprising at least one Y-bit portion. At least two partial products are generated, each partial product comprising a product of a selected X-bit portion of the first operand and a selected Y-bit portion of the second operand. Each partial product is converted to a redundant representation in dependence on significance indicating information indicative of a significance of the partial product. In the redundant representation, the partial product is represented using a number of N-bit portions, and in a group of at least two adjacent N-bit portions, a number of overlap bits of a lower N-bit portion of the group have a same significance as some least significant bits of at least one upper N-bit portion of the group. The partial products are added while represented in the redundant representation.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 11, 2017
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess, Christopher Neal Hinds
  • Patent number: 9703529
    Abstract: A data processing system performs processing operations upon input operand(s) having a programmable bit significance. Exception generating circuitry generates exception indications representing exceptions such as overflow, underflow and inexact in respect of a result value having the programmable bit significance.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: July 11, 2017
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess, Christopher Neal Hinds
  • Patent number: 9696964
    Abstract: A floating point multiply add circuit 24 includes a multiplier 26 and an adder 28. The input operands A, B and C together with the result value all have a normal exponent value range, such as a range consistent with the IEEE Standard 754. The product value which is passed from the multiplier 26 to the adder 28 as an extended exponent value range that extents lower than the normal exponent value range. Shifters 48, 50 within the adder can take account of the extended exponent value range of the product as necessary in order to bring the result value back into the normal exponent value range.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: July 4, 2017
    Assignee: ARM Limited
    Inventors: David Raymond Lutz, Neil Burgess