Abstract: A data processing apparatus includes floating-point adder circuitry and floating-point conversion circuitry that generates a floating-point number as an output by performing a conversion on any input having a format from a list of formats including: an integer number, a fixed-point number, and a floating-point number having a format smaller than the output floating-point number. The floating-point conversion circuitry is physically distinct from the floating-point adder circuitry.

Abstract: A data processing apparatus has permutation circuitry for performing a permutation operation for changing a data element size or data element positioning of at least one source operand to generate first and second SIMD operands, and SIMD processing circuitry for performing a SIMD operation on the first and second SIMD operands. In response to a first SIMD instruction requiring a permutation operation, the instruction decoder controls the permutation circuitry to perform the permutation operation to generate the first and second SIMD operands and then controls the SIMD processing circuitry to perform the SIMD operation using these operands. In response to a second SIMD instruction not requiring a permutation operation, the instruction decoder controls the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands identified by the instruction, without passing them via the permutation circuitry.

Abstract: Apparatus for data processing and a method of data processing are provided. Shift circuitry performs a shift operation in response to a shift instruction, shifting bits of an input data value in a direction specified by the shift instruction. Bit location indicator generation circuitry and comparison circuitry operate in parallel with the shift circuitry. The bit location indicator indicates at least one bit location in the input data value which must not have a bit set if the shifted data value is not to saturate. Comparison circuitry compares the bit location indicator with the input data value and indicates a saturation condition if any bits are indicated by the bit position indicator for bit locations which hold set bits in the input data value. A faster indication of the saturation condition thus results.

Abstract: A processing apparatus supports a narrowing-and-rounding arithmetic operation which generates, in response to two operands each comprising at least one W-bit data element, a result value comprising at least one X-bit result data element, with each X-bit result data element representing a sum or difference of corresponding W-bit data elements of the two operands rounded to an X-bit value (W>X). The arithmetic operation is implemented using a number of N-bit additions (N<W), with carry values from a first stage of N-bit additions being added at a second stage of N-bit additions for adding a rounding value to the result of the first stage additions. This technique reduces the amount of time required for performing the narrowing-and-rounding arithmetic operation.

Abstract: A data processing apparatus has a processing circuitry for performing a floating-point square root operation on a radicand value R to generate a result value. The processing circuitry has first square root processing circuitry for processing radicand values R which are not an exact power of two and second square root processing circuitry for processing radicand values which are an exact power of 2. Power-of-two detection circuitry detects whether the radicand value is an exact power of two and selects the output of the first or second square root processing circuitry as appropriate. This allows the result to be generated in fewer processing cycles when the radicand is a power of 2.

Abstract: A data processing apparatus and method of operating such a data processing apparatus are provided, for responding to a division instruction to perform a division operation to generate a result value by dividing an input numerator specified by the division instruction by an input denominator specified by the division instruction. The input numerator and input denominator are binary values. The apparatus comprises division circuitry configured to generate the result value by carrying out the division operation, power-of-two detection circuitry configured to signal a bypass condition if the input denominator has a value given by ±2N, where N is a positive integer, and bypass circuitry configured, in response to signalling of the bypass condition, to cause the division circuitry to be bypassed and to cause the result value to be generated as the input numerator shifted by N bits.

Abstract: Apparatus for data processing and a method of data processing are provided. Shift circuitry performs a shift operation in response to a shift instruction, shifting bits of an input data value in a direction specified by the shift instruction. Bit location indicator generation circuitry and comparison circuitry operate in parallel with the shift circuitry. The bit location indicator indicates at least one bit location in the input data value which must not have a bit set if the shifted data value is not to saturate. Comparison circuitry compares the bit location indicator with the input data value and indicates a saturation condition if any bits are indicated by the bit position indicator for bit locations which hold set bits in the input data value. A faster indication of the saturation condition thus results.

Abstract: Apparatus for data processing and a method of data processing are provided. Shift circuitry performs a shift operation in response to a shift instruction, shifting bits of an input data value in a direction specified by the shift instruction. Bit location indicator generation circuitry and comparison circuitry operate in parallel with the shift circuitry. The bit location indicator indicates at least one bit location in the input data value which must not have a bit set if the shifted data value is not to saturate. Comparison circuitry compares the bit location indicator with the input data value and indicates a saturation condition if any bits are indicated by the bit position indicator for bit locations which hold set bits in the input data value. A faster indication of the saturation condition thus results.

Abstract: A data processing apparatus and method are provided for performing a shift function on a binary number. The apparatus comprises count determination circuitry for determining a number of contiguous bit positions in the binary number that have a predetermined bit value, the count determination circuitry outputting a count value indicative of the number of contiguous bit positions determined. In parallel with the operation of the count determination circuitry, coarse shifting circuitry is used to determine, for at least one predetermined number of contiguous bit positions, whether that predetermined number of contiguous bit positions within the binary number has said predetermined bit value. An initial shift operation is then performed on the binary number based on that determination in order to produce an intermediate binary number.

Abstract: A data processing apparatus and method are provided for multiplying first and second normalised floating point operands in order to generate a result, each normalised floating point operand comprising a significand and an exponent. Exponent determination circuitry is used to compute a result exponent for a normalised version of the result, and rounding value generation circuitry then generates a rounding value by shifting a rounding constant in a first direction by a shift amount that is dependent on the result exponent. Partial product generation circuitry multiplies the significands of the first and second normalised floating point operands to generate the first and second partial products, and the first and second partial products are then added together, along with the rounding value, in order to generate a normalised result significand.

Abstract: Processing circuitry 2 is provided for comparing a number of adjacent widths having a common value and extending from a starting position within an input number with a runlength specified by a variable number. The circuitry includes a mask generator 22 for generating a mask value in dependence upon the variable number, combination circuitry 24 for performing a logical combination operation upon respective bits within the input number starting from the starting position and corresponding bits within the mask value so as to generate an intermediate value. Result circuitry 26 then generates a result indicative of whether or not the number of adjacent bits is less than or equal to the run length in dependence upon a determination if any bits within the intermediate value have a predetermined value.

Abstract: Processing circuitry is provided to perform an operation FRINT for rounding a floating-point value to an integral floating-point value. Control circuitry controls the processing circuitry to perform the FRINT operation in response to an FRINT instruction. The processing circuitry includes shifting circuitry for generating a rounding value by shifting a base value, adding circuitry for adding the rounding value to the significand of the floating-point value to generate a sum value, mask generating circuitry for generating a mask for clearing fractional-valued bits of the sum value, and masking circuitry for applying the mask to the sum value to generate the integral floating-point value.

Abstract: A floating point multiply add circuit 24 includes a multiplier 26 and an adder 28. The input operands A, B and C together with the result value all have a normal exponent value range, such as a range consistent with the IEEE Standard 754. The product value which is passed from the multiplier 26 to the adder 28 as an extended exponent value range that extents lower than the normal exponent value range. Shifters 48, 50 within the adder can take account of the extended exponent value range of the product as necessary in order to bring the result value back into the normal exponent value range.

Abstract: A data processing apparatus includes processing circuitry for performing a convert-to-integer operation for converting a floating-point value to a rounded two's complement integer value. The convert-to-integer operation uses round-to-nearest, ties away from zero, rounding (RNA rounding). The operation is performed by generating an intermediate value based on the floating-point value, adding a rounding value to the intermediate value to generate a sum value, and outputting the integer-valued bits of the sum value as the rounded two's complement integer value. If the floating-point value is negative, then the intermediate value is generated by inverting the bits without adding a bit value of 1 to a least significant bit of the inverted value.

Abstract: A processing apparatus supports a narrowing-and-rounding arithmetic operation which generates, in response to two operands each comprising at least one W-bit data element, a result value comprising at least one X-bit result data element, with each X-bit result data element representing a sum or difference of corresponding W-bit data elements of the two operands rounded to an X-bit value (W>X). The arithmetic operation is implemented using a number of N-bit additions (N<W), with carry values from a first stage of N-bit additions being added at a second stage of N-bit additions for adding a rounding value to the result of the first stage additions. This technique reduces the amount of time required for performing the narrowing-and-rounding arithmetic operation.

Abstract: A lookup table receives an n-bit input value and returns an output value that would be obtained by performance of a predetermined operation on the input value. The number of entries in the lookup table is less than 2n. An n-bit input data value is received, a modification condition is detected if any of a predetermined number of significant bits of the input data value are logic zeroes, and a shift operation is performed on the input data value if the modification condition is detected, prior to providing the input to the lookup table. If the modification condition is detected, an output value derivation operation is performed on the output value received from the lookup table to modify it prior to returning it to for processing. The derivation operation accounts for the shift operation. This approach can lead to a significant reduction in the lookup table size.

Abstract: A data processing apparatus has permutation circuitry for performing a permutation operation for changing a data element size or data element positioning of at least one source operand to generate first and second SIMD operands, and SIMD processing circuitry for performing a SIMD operation on the first and second SIMD operands. In response to a first SIMD instruction requiring a permutation operation, the instruction decoder controls the permutation circuitry to perform the permutation operation to generate the first and second SIMD operands and then controls the SIMD processing circuitry to perform the SIMD operation using these operands. In response to a second SIMD instruction not requiring a permutation operation, the instruction decoder controls the SIMD processing circuitry to perform the SIMD operation using the first and second SIMD operands identified by the instruction, without passing them via the permutation circuitry.

Abstract: Processing circuitry is provided for performing a shift-round-and-accumulate operation. The operation comprises shifting an input value to generate a shifted value using shifting circuitry, adding the shifted value to an accumulate value using adding circuitry, and performing rounding by adding a rounding value to the sum of the shifted value and the accumulated value using the adding circuitry. The same adding circuitry is used to perform both the addition of the shifted value and the accumulated value and the addition of the rounding value in the same processing cycle.

Abstract: A data processing apparatus is provided with lookup table circuitry for receiving from the processing circuitry an n-bit input data value, and for returning to the processing circuitry an output data value. The lookup table circuitry provides a plurality of entries identifying possible input data values and corresponding output data values, with the plurality of entries being less than 2n. Input interface circuitry receives the n-bit input data value, detects a modification condition if any of a predetermined number of significant bits of the input data value are logic zero values, and performs a shift operation on the input data value if the modification condition is detected, prior to providing the input to the lookup table. Output interface circuitry is then arranged, if the modification condition is detected, to perform an output data value derivation operation on the output data value as received from the lookup table.

Abstract: Processing circuitry is provided for performing a shift-round-and-accumulate operation. The operation comprises shifting an input value to generate a shifted value using shifting circuitry, adding the shifted value to an accumulate value using adding circuitry, and performing rounding by adding a rounding value to the sum of the shifted value and the accumulated value using the adding circuitry. The same adding circuitry is used to perform both the addition of the shifted value and the accumulated value and the addition of the rounding value in the same processing cycle.