Abstract: In the proposed method of generating a pulsed output signal from a periodic ramp signal and a reference voltage, the linear range of duty cycles of the pulsed output signal is significantly extended to minimum values. The ramp signal and the reference voltage are applied to inputs of a comparator and the output signal is taken from an output of the comparator. The ramp signal has a ramp that extends between a minimum voltage level and a maximum voltage level. The duty cycle of the pulse signal is controlled by varying the reference voltage between the minimum and maximum voltage levels. The ramp has an initial start section extending from the minimum voltage level and a main section extending between the initial section and the maximum voltage level. The ramp slope has a constant value over the main ramp section and a value greater than the constant value over the initial section.

Abstract: A switch mode power converter is provided which includes a switching cell with a supply input, an output and a control input. A summing comparator has first and second differential input pairs and an output. The output is connected to the control input of the switching cell. An oscillator provides a periodic waveform that is applied to a first one of the inputs of the first differential input pair of the summing comparator. An adjustable reference voltage source provides an adjustable reference voltage a predetermined fraction of which is applied to a second one of the inputs of the first differential input pair of the summing comparator. An error amplifier has differential outputs coupled to the second pair of differential inputs of the summing comparator and a differential input pair.

Abstract: A method for the detection of a target nucleic acid, which method comprises contacting template nucleic acid from a sample with (i) a signalling system and (ii) a tailed nucleic acid primer having a template binding region and the tail comprising a linker and a target binding region, in the presence of appropriate nucleoside triphosphates and an agent for polymerisation thereof, under conditions such that the template binding region of the primer will hybridise to a complementary sequence in the template nucleic acid and be extended to form a primer extension product, separating any such product from the template whereupon the target binding region in the tail of the primer will hybridise to a sequence in the primer extension product corresponding to the target nucleic acid, and wherein any such target specific hybridisation causes a detectable change in the signalling system, such that the presence or absence of the target nucleic acid in the sample is detected by reference to the presence or absence of a de

Abstract: The present invention provides an ultra linear, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage disclosed is significantly higher linearity for the same supply current, or equivalent linearity using a lower supply current. The present invention achieves this using an pre-driver sub-stage (122) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage (123). The output of the disclosed operational amplifier output stage takes the form; &dgr;Io≈&bgr;n*&bgr;p*&dgr;Iin. When used with a localized feedback circuitry, bandwidth is extended.

Abstract: This invention relates to aryl urea compounds in combination with cytotoxic or cytostatic agents for use in treating raf kinase mediated diseases such as cancer.

Abstract: The present invention provides an high beta, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage over conventional methods disclosed is up to &bgr;2 rather than a single beta. The present invention achieves this using an pre-driver sub-stage (122) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage (123). The output of the disclosed operational amplifier output stage takes the form: &dgr;Io≈&bgr;n*&bgr;p*&dgr;Iin. When used with a localized feedback circuitry, speed performance is increased and bandwidth is extended.

Abstract: The present invention provides an high beta, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage over conventional methods disclosed is up to &bgr;2 rather than a single beta. The present invention achieves this using an pre-driver sub-stage (122) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage (123).

Abstract: The present invention provides an ultra linear, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage disclosed is significantly higher linearity for the same supply current, or equivalent linearity using a lower supply current. The present invention achieves this using an pre-driver sub-stage (122) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage (123). The output of the disclosed operational amplifier output stage takes the form; &dgr;Io≈&bgr;n*&bgr;p*&dgr;Iin. When used with a localized feedback circuitry, bandwidth is extended.

Abstract: An upstream programmable gain amplifier (PGA) (114, 214) for a cable modem (100) having a programmable bias current. PGA (114, 214) includes a bias current-setting circuit (140, 240) coupled to a power amplifier stage (136, 236), the bias current-setting circuit (140, 240) adapted to program the bias current Ibias of the power amplifier stage (136, 236). The bias current-setting circuit (140) includes a bandgap generator (130, 230) having an external bias resistor R1 at the input. The bias current-setting circuit (140) may include a variable gain amplifier (VGA) (134), a digital-to-analog converter (DAC) (132), and a bias code generator (138). The bias current-setting circuit (240) may alternatively include a plurality of programmable resistors R1a, R1b . . . R1x coupled to a bias code generator (238).

Abstract: The present invention provides technical advantages as a class AB output driver (400) with minimal cross-over distortion. If the differential input to the driver is I+&dgr;I/2 and I−&dgr;I/2, then the current gain is the average of &bgr;n and &bgr;p, more specifically, (&bgr;n−&bgr;p)*I+((&bgr;n+&bgr;p)/2)* &dgr;I. The offset current (&bgr;n−&bgr;p)*I is taken out with a feedback loop.

Abstract: A programmable gain amplifier (10) has a differential input (12-13), a differential output (16-17), and a plurality of enable inputs (21, 31-34). The amplifier includes a plurality of transconductor sections (26-29), which each have input nodes coupled to the differential input, output nodes coupled to the differential output, and an enable node coupled to a respective enable signal. The transconductor sections have different gains, which are respective powers of two. Each transconductor section includes a transconductor circuit (51, 56) which is coupled in series with at least one current mirror circuit (52-53, 57-58). Each transconductor circuit has a transistor (121) with a class A quiescent current that is proportional to the corresponding gain, the transistor being sized to achieve an optimum current density for its quiescent current.

Abstract: A method for adjusting the output response of a complementary bipolar operational amplifier includes: providing a first bipolar transistor 14; providing a second bipolar transistor 16 coupled to the first bipolar transistor 14; providing a first current source 26 coupled to a base of the first bipolar transistor 14; providing a second current source 28 coupled to a base of the second bipolar transistor 16; providing a third bipolar transistor 10 coupled to the base of the first bipolar transistor 14; providing a fourth bipolar transistor 12 coupled to the base of the second bipolar transistor 16; providing a first resistor 20 coupled between a base of the third transistor 10 and a common node; providing a second resistor 18 coupled between a base of the fourth transistor 12 and the common node; providing a capacitor 30 coupled to the common node; providing a first input stage current source 24 coupled to the first resistor 20; providing a second input stage current source 22 coupled to the fourth resistor 18;

Abstract: A low EMI bias current generator for cable modem applications has a distributed output stage with a steering input that controls the amount of bias current flowing through each transistor of a differential pair. A pair of resistors acts as a potentiometer controlling the amount of voltage seen across the input of the differential pair. The resistor pair controls the speed of transfer of bias current from one transistor to another such that the current transfer will take the form of a hyperbolic tangent that will allow a very gentle start-up.

Abstract: A current-to-current impedance converter re-circulates the driver transistor collector current back into the output current path to generate an error current that has two portions including a DC offset portion and a second order in 1/&bgr; portion. Since the error current has no first order in 1/&bgr; portion, the current-to-current ronverter exhbits very low distortion.

Abstract: An output stage of a complementary bipolar operational amplifier includes: a first bipolar transistor 14; a second bipolar transistor 16 coupled to the first bipolar transistor 14; a third bipolar transistor 10; a fourth bipolar transistor 12; a first resistor 42 coupled between a base of the first bipolar transistor 14 and the third bipolar transistor 10; a second resistor 43 coupled between a base of the second bipolar transistor 16 and the fourth bipolar transistor 12; a first current source 26; a second current source 28; a third resistor 40 coupled between the first current source 26 and the third transistor 10; a fourth resistor 41 coupled between the second current source 28 and the fourth transistor 12; a fifth resistor 19 coupled between a base of the third transistor 10 and a common node; a sixth resistor 18 coupled between a base of the fourth transistor 12 and the common node; a first input stage current source 24 coupled to the base of the third transistor 10; and a second input stage current sou

Abstract: A programmable gain amplifier (10) has a differential input (12-13), a differential output (16-17), and a plurality of enable inputs (21, 31-34). The amplifier includes a plurality of transconductor sections (26-29), which each have input nodes coupled to the differential input, output nodes coupled to the differential output, and an enable node coupled to a respective enable signal. The transconductor sections have different gains, which are respective powers of two. Each transconductor section includes a transconductor circuit (51, 56) which is coupled in series with at least one current mirror circuit (52-53, 57-58). Each transconductor circuit has a transistor (121) with a class A quiescent current that is proportional to the corresponding gain, the transistor being sized to achieve an optimum current density for its quiescent current.

Abstract: A controller for a power converter wherein there is provided a comparator having an output terminal and first and second input terminals. A switch-mode power train is coupled to the output terminal and operable to receive an unregulated input voltage and provide a regulated output voltage. A feedback network coupled to the switch-mode power train provides a voltage to the first input of the comparator. A ramp circuit includes a first capacitor divider having a first capacitor connected from a first input node to a first midpoint node and a second capacitor connected from the first midpoint node to a first reference voltage node and a second capacitor divider including a third capacitor connected from a second input node to a second midpoint node and a fourth capacitor connected from the second midpoint node to the first reference node. A first switch couples the first or second midpoint node to the second input of said comparator.

Abstract: A boost mode controller with start up circuit includes: an inductor 12; a transistor 10 coupled to a first end of the inductor 12; a diode 16 having an anode coupled to the first end of the inductor 12; a capacitor 14 coupled to a cathode of the diode 16; a logic circuit 22 having an output coupled to a control node of the transistor 10; a comparator 28 having an output coupled to a first input of the logic circuit 22, a first input of the comparator 28 coupled to the capacitor 14, and a second input of the comparator 28 coupled to a reference node; and a counter 20 having an active low reset coupled to the output of the comparator 28 and an output coupled to a second input of the logic circuit 22.