Patents by Inventor Neil Quinn

Neil Quinn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250133774
    Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.
    Type: Application
    Filed: December 27, 2024
    Publication date: April 24, 2025
    Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang, Feng-Cheng Yang, Neil Quinn Murray
  • Patent number: 12283635
    Abstract: A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.
    Type: Grant
    Filed: February 20, 2024
    Date of Patent: April 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Katherine H. Chiang, Neil Quinn Murray, Ming-Yen Chuang, Chung-Te Lin
  • Patent number: 12261222
    Abstract: The present disclosure relates to a method of manufacturing a semiconductor structure. The method may be performed by forming a first source/drain region. A first dielectric layer is formed above the first source/drain region. A portion of the first dielectric layer is removed. A channel region is formed along a sidewall of the first dielectric layer. A gate region is formed along a sidewall of the channel region. A second dielectric layer is formed above the first dielectric layer and the gate region. A portion of the second dielectric layer is removed to form an opening that exposes the channel region. A second source/drain region is formed within the opening.
    Type: Grant
    Filed: November 2, 2023
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neil Quinn Murray, Katherine H. Chiang, Chung-Te Lin
  • Publication number: 20250089294
    Abstract: A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate.
    Type: Application
    Filed: November 22, 2024
    Publication date: March 13, 2025
    Inventors: Neil Quinn Murray, Mauricio Manfrini, Hung-Wei Li
  • Patent number: 12218250
    Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang, Feng-Cheng Yang, Neil Quinn Murray
  • Patent number: 12215763
    Abstract: A drive train, including: a first electric motor; a second electric motor; and a transmission system including a first input shaft driveably connected to the first electric motor, a second input shaft driveably connected to the second electric motor, a first gear train including a first gear element rotatably mounted on the first input shaft and a second gear element rotatably mounted on the second input shaft, a second gear train including a third gear element rotatably mounted on the first input shaft and a fourth gear element rotatably mounted on the second input shaft, a gear selector assembly arranged to selectively lock either the first and third gear elements for rotation with the first input shaft or the second and fourth gear elements for rotation with the second input shaft.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: February 4, 2025
    Assignee: ZEROSHIFT TRANSMISSIONS LIMITED
    Inventor: Neil Quinn
  • Patent number: 12183825
    Abstract: A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Neil Quinn Murray, Mauricio Manfrini, Hung-Wei Li
  • Publication number: 20240194796
    Abstract: A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.
    Type: Application
    Filed: February 20, 2024
    Publication date: June 13, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Katherine H. CHIANG, Neil Quinn MURRAY, Ming-Yen CHUANG, Chung-Te LIN
  • Publication number: 20240178322
    Abstract: A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Neil Quinn Murray, Mauricio Manfrini, Hung-Wei Li
  • Publication number: 20240106029
    Abstract: A battery pack (1) comprises one or more battery modules (10). A battery module (10) comprises one or more cells (120) and a thermal management arrangement (140) for thermally managing the one or more cells (120). The thermal management arrangement (140) comprises at least one thermal management duct (141), an intake-side fluid delivery arrangement (200c) and an outlet-side fluid delivery arrangement (200d). The inlet-side fluid delivery arrangement (200c) is in fluid communication with the outlet-side fluid delivery arrangement (200d) via the at least one thermal management duct (141). Each fluid delivery arrangement (200) comprises first and second fluid connection arrangements for allowing a thermal management fluid to enter and/or exit the thermal management arrangement (140).
    Type: Application
    Filed: January 27, 2022
    Publication date: March 28, 2024
    Inventors: Barry FLANNERY, Sean MCFADDEN, Meaghan COLLINS, Neil QUINN
  • Publication number: 20240097041
    Abstract: A thin film transistor, a semiconductor device having a thin film transistor and a method of fabricating a thin film transistor are provided. The thin film transistor includes a gate metal; a gate dielectric layer disposed on the gate metal; a semiconductor layer disposed on the gate dielectric layer; an interlayer dielectric disposed on the semiconductor layer and having a contact hole over the semiconductor layer; a source/drain metal disposed in the contact hole; a first liner disposed between the interlayer dielectric and the source/drain metal; and a second liner disposed between the first liner and the source/drain metal and being in contact with the semiconductor layer in the contact hole.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neil Quinn Murray, Hung-Wei Li, Mauricio MANFRINI, Sai-Hooi Yeong
  • Patent number: 11935966
    Abstract: A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Katherine H. Chiang, Neil Quinn Murray, Ming-Yen Chuang, Chung-Te Lin
  • Publication number: 20240063307
    Abstract: The present disclosure relates to a method of manufacturing a semiconductor structure. The method may be performed by forming a first source/drain region. A first dielectric layer is formed above the first source/drain region. A portion of the first dielectric layer is removed. A channel region is formed along a sidewall of the first dielectric layer. A gate region is formed along a sidewall of the channel region. A second dielectric layer is formed above the first dielectric layer and the gate region. A portion of the second dielectric layer is removed to form an opening that exposes the channel region. A second source/drain region is formed within the opening.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Inventors: Neil Quinn Murray, Katherine H. Chiang, Chung-Te Lin
  • Patent number: 11873866
    Abstract: A transmission system including a first gear rotatably mounted on an input shaft; a second gear mounted on a lay shaft; a selector that selectively locks first and second gears for rotation with the input shaft and includes a single engagement ring with a first side having a first set of engagement elements each having a drive face that drivingly engages in a first rotational direction a first set of drive formations of the first gear and a non-driving face that slips with respect to the first set of drive formations in a second rotational direction, and a second side having a second set of engagement elements each having a drive face that drivingly engages in the second rotational direction a second set of drive formations of the second gear and a non-driving face that slips with respect to the second set of drive formations in the first rotational direction.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: January 16, 2024
    Assignee: ZEROSHIFT TRANSMISSIONS LIMITED
    Inventor: Neil Quinn
  • Patent number: 11855226
    Abstract: A thin film transistor, a semiconductor device having a thin film transistor and a method of fabricating a thin film transistor are provided. The thin film transistor includes a gate metal; a gate dielectric layer disposed on the gate metal; a semiconductor layer disposed on the gate dielectric layer; an interlayer dielectric disposed on the semiconductor layer and having a contact hole over the semiconductor layer; a source/drain metal disposed in the contact hole; a first liner disposed between the interlayer dielectric and the source/drain metal; and a second liner disposed between the first liner and the source/drain metal and being in contact with the semiconductor layer in the contact hole.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neil Quinn Murray, Hung-Wei Li, Mauricio Manfrini, Sai-Hooi Yeong
  • Patent number: 11843056
    Abstract: A semiconductor structure is provided. The semiconductor structure may include a transistor structure, the transistor structure may include a gate region arranged over an upper surface of a substrate and extending substantially in a first direction that is perpendicular to the upper surface of the substrate; a first source/drain region over the upper surface of the substrate; a second source/drain region over the upper surface of the substrate; and a channel region vertically extending in the first direction between the first source/drain region and the second source/drain region, wherein the channel region comprises an oxide semiconductor material. Along the first direction, the gate region covers a sidewall of the channel region.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neil Quinn Murray, Katherine H. Chiang, Chung-Te Lin
  • Publication number: 20230369438
    Abstract: A transistor includes a gate electrode, a gate dielectric layer, a short range order layer, a channel layer, and source/drain regions. The gate dielectric layer is disposed over the gate electrode. The short range order layer is disposed between the gate electrode and the gate dielectric layer. The short ranger order layer has slanted sidewalls. The channel layer is disposed on the gate dielectric layer. The source/drain regions are disposed on the channel layer.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Neil Quinn Murray, Kuo-Chang Chiang, Mauricio MANFRINI, Tsann Lin
  • Publication number: 20230327024
    Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.
    Type: Application
    Filed: June 14, 2023
    Publication date: October 12, 2023
    Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang, Feng-Cheng Yang, Neil Quinn Murray
  • Patent number: 11721767
    Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo Chiang, Hung-Chang Sun, TsuChing Yang, Sheng-Chih Lai, Yu-Wei Jiang, Feng-Cheng Yang, Neil Quinn Murray
  • Publication number: 20230062099
    Abstract: A drive train, including: a first electric motor; a second electric motor; and a transmission system including a first input shaft driveably connected to the first electric motor, a second input shaft driveably connected to the second electric motor, a first gear train including a first gear element rotatably mounted on the first input shaft and a second gear element rotatably mounted on the second input shaft, a second gear train including a third gear element rotatably mounted on the first input shaft and a fourth gear element rotatably mounted on the second input shaft, a gear selector assembly arranged to selectively lock either the first and third gear elements for rotation with the first input shaft or the second and fourth gear elements for rotation with the second input shaft.
    Type: Application
    Filed: February 6, 2020
    Publication date: March 2, 2023
    Inventor: Neil QUINN