Patents by Inventor Neil Quinn
Neil Quinn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250133774Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.Type: ApplicationFiled: December 27, 2024Publication date: April 24, 2025Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang, Feng-Cheng Yang, Neil Quinn Murray
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Patent number: 12283635Abstract: A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.Type: GrantFiled: February 20, 2024Date of Patent: April 22, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Katherine H. Chiang, Neil Quinn Murray, Ming-Yen Chuang, Chung-Te Lin
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Patent number: 12261222Abstract: The present disclosure relates to a method of manufacturing a semiconductor structure. The method may be performed by forming a first source/drain region. A first dielectric layer is formed above the first source/drain region. A portion of the first dielectric layer is removed. A channel region is formed along a sidewall of the first dielectric layer. A gate region is formed along a sidewall of the channel region. A second dielectric layer is formed above the first dielectric layer and the gate region. A portion of the second dielectric layer is removed to form an opening that exposes the channel region. A second source/drain region is formed within the opening.Type: GrantFiled: November 2, 2023Date of Patent: March 25, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neil Quinn Murray, Katherine H. Chiang, Chung-Te Lin
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Publication number: 20250089294Abstract: A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate.Type: ApplicationFiled: November 22, 2024Publication date: March 13, 2025Inventors: Neil Quinn Murray, Mauricio Manfrini, Hung-Wei Li
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Patent number: 12218250Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.Type: GrantFiled: June 14, 2023Date of Patent: February 4, 2025Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang, Feng-Cheng Yang, Neil Quinn Murray
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Patent number: 12215763Abstract: A drive train, including: a first electric motor; a second electric motor; and a transmission system including a first input shaft driveably connected to the first electric motor, a second input shaft driveably connected to the second electric motor, a first gear train including a first gear element rotatably mounted on the first input shaft and a second gear element rotatably mounted on the second input shaft, a second gear train including a third gear element rotatably mounted on the first input shaft and a fourth gear element rotatably mounted on the second input shaft, a gear selector assembly arranged to selectively lock either the first and third gear elements for rotation with the first input shaft or the second and fourth gear elements for rotation with the second input shaft.Type: GrantFiled: February 6, 2020Date of Patent: February 4, 2025Assignee: ZEROSHIFT TRANSMISSIONS LIMITEDInventor: Neil Quinn
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Patent number: 12183825Abstract: A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate.Type: GrantFiled: February 5, 2024Date of Patent: December 31, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Neil Quinn Murray, Mauricio Manfrini, Hung-Wei Li
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Publication number: 20240194796Abstract: A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.Type: ApplicationFiled: February 20, 2024Publication date: June 13, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Katherine H. CHIANG, Neil Quinn MURRAY, Ming-Yen CHUANG, Chung-Te LIN
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Publication number: 20240178322Abstract: A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate.Type: ApplicationFiled: February 5, 2024Publication date: May 30, 2024Inventors: Neil Quinn Murray, Mauricio Manfrini, Hung-Wei Li
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Publication number: 20240106029Abstract: A battery pack (1) comprises one or more battery modules (10). A battery module (10) comprises one or more cells (120) and a thermal management arrangement (140) for thermally managing the one or more cells (120). The thermal management arrangement (140) comprises at least one thermal management duct (141), an intake-side fluid delivery arrangement (200c) and an outlet-side fluid delivery arrangement (200d). The inlet-side fluid delivery arrangement (200c) is in fluid communication with the outlet-side fluid delivery arrangement (200d) via the at least one thermal management duct (141). Each fluid delivery arrangement (200) comprises first and second fluid connection arrangements for allowing a thermal management fluid to enter and/or exit the thermal management arrangement (140).Type: ApplicationFiled: January 27, 2022Publication date: March 28, 2024Inventors: Barry FLANNERY, Sean MCFADDEN, Meaghan COLLINS, Neil QUINN
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Publication number: 20240097041Abstract: A thin film transistor, a semiconductor device having a thin film transistor and a method of fabricating a thin film transistor are provided. The thin film transistor includes a gate metal; a gate dielectric layer disposed on the gate metal; a semiconductor layer disposed on the gate dielectric layer; an interlayer dielectric disposed on the semiconductor layer and having a contact hole over the semiconductor layer; a source/drain metal disposed in the contact hole; a first liner disposed between the interlayer dielectric and the source/drain metal; and a second liner disposed between the first liner and the source/drain metal and being in contact with the semiconductor layer in the contact hole.Type: ApplicationFiled: November 23, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neil Quinn Murray, Hung-Wei Li, Mauricio MANFRINI, Sai-Hooi Yeong
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Patent number: 11935966Abstract: A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.Type: GrantFiled: April 28, 2021Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Katherine H. Chiang, Neil Quinn Murray, Ming-Yen Chuang, Chung-Te Lin
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Publication number: 20240063307Abstract: The present disclosure relates to a method of manufacturing a semiconductor structure. The method may be performed by forming a first source/drain region. A first dielectric layer is formed above the first source/drain region. A portion of the first dielectric layer is removed. A channel region is formed along a sidewall of the first dielectric layer. A gate region is formed along a sidewall of the channel region. A second dielectric layer is formed above the first dielectric layer and the gate region. A portion of the second dielectric layer is removed to form an opening that exposes the channel region. A second source/drain region is formed within the opening.Type: ApplicationFiled: November 2, 2023Publication date: February 22, 2024Inventors: Neil Quinn Murray, Katherine H. Chiang, Chung-Te Lin
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Patent number: 11873866Abstract: A transmission system including a first gear rotatably mounted on an input shaft; a second gear mounted on a lay shaft; a selector that selectively locks first and second gears for rotation with the input shaft and includes a single engagement ring with a first side having a first set of engagement elements each having a drive face that drivingly engages in a first rotational direction a first set of drive formations of the first gear and a non-driving face that slips with respect to the first set of drive formations in a second rotational direction, and a second side having a second set of engagement elements each having a drive face that drivingly engages in the second rotational direction a second set of drive formations of the second gear and a non-driving face that slips with respect to the second set of drive formations in the first rotational direction.Type: GrantFiled: September 2, 2019Date of Patent: January 16, 2024Assignee: ZEROSHIFT TRANSMISSIONS LIMITEDInventor: Neil Quinn
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Patent number: 11855226Abstract: A thin film transistor, a semiconductor device having a thin film transistor and a method of fabricating a thin film transistor are provided. The thin film transistor includes a gate metal; a gate dielectric layer disposed on the gate metal; a semiconductor layer disposed on the gate dielectric layer; an interlayer dielectric disposed on the semiconductor layer and having a contact hole over the semiconductor layer; a source/drain metal disposed in the contact hole; a first liner disposed between the interlayer dielectric and the source/drain metal; and a second liner disposed between the first liner and the source/drain metal and being in contact with the semiconductor layer in the contact hole.Type: GrantFiled: July 30, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neil Quinn Murray, Hung-Wei Li, Mauricio Manfrini, Sai-Hooi Yeong
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Patent number: 11843056Abstract: A semiconductor structure is provided. The semiconductor structure may include a transistor structure, the transistor structure may include a gate region arranged over an upper surface of a substrate and extending substantially in a first direction that is perpendicular to the upper surface of the substrate; a first source/drain region over the upper surface of the substrate; a second source/drain region over the upper surface of the substrate; and a channel region vertically extending in the first direction between the first source/drain region and the second source/drain region, wherein the channel region comprises an oxide semiconductor material. Along the first direction, the gate region covers a sidewall of the channel region.Type: GrantFiled: July 16, 2021Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neil Quinn Murray, Katherine H. Chiang, Chung-Te Lin
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Publication number: 20230369438Abstract: A transistor includes a gate electrode, a gate dielectric layer, a short range order layer, a channel layer, and source/drain regions. The gate dielectric layer is disposed over the gate electrode. The short range order layer is disposed between the gate electrode and the gate dielectric layer. The short ranger order layer has slanted sidewalls. The channel layer is disposed on the gate dielectric layer. The source/drain regions are disposed on the channel layer.Type: ApplicationFiled: May 10, 2022Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Neil Quinn Murray, Kuo-Chang Chiang, Mauricio MANFRINI, Tsann Lin
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Publication number: 20230327024Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.Type: ApplicationFiled: June 14, 2023Publication date: October 12, 2023Inventors: Kuo-Chang Chiang, Hung-Chang Sun, Sheng-Chih Lai, TsuChing Yang, Yu-Wei Jiang, Feng-Cheng Yang, Neil Quinn Murray
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Patent number: 11721767Abstract: A transistor including a channel layer including an oxide semiconductor material and methods of making the same. The transistor includes a channel layer having a first oxide semiconductor layer having a first oxygen concentration, a second oxide semiconductor layer having a second oxygen concentration and a third oxide semiconductor layer having a third oxygen concentration. The second oxide semiconductor layer is located between the first semiconductor oxide layer and the third oxide semiconductor layer. The second oxygen concentration is lower than the first oxygen concentration and the third oxygen concentration.Type: GrantFiled: April 14, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuo Chiang, Hung-Chang Sun, TsuChing Yang, Sheng-Chih Lai, Yu-Wei Jiang, Feng-Cheng Yang, Neil Quinn Murray
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Publication number: 20230062099Abstract: A drive train, including: a first electric motor; a second electric motor; and a transmission system including a first input shaft driveably connected to the first electric motor, a second input shaft driveably connected to the second electric motor, a first gear train including a first gear element rotatably mounted on the first input shaft and a second gear element rotatably mounted on the second input shaft, a second gear train including a third gear element rotatably mounted on the first input shaft and a fourth gear element rotatably mounted on the second input shaft, a gear selector assembly arranged to selectively lock either the first and third gear elements for rotation with the first input shaft or the second and fourth gear elements for rotation with the second input shaft.Type: ApplicationFiled: February 6, 2020Publication date: March 2, 2023Inventor: Neil QUINN