Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Abstract: Disclosed is, a method for detecting electrical defects on test structures of a semiconductor die. The semiconductor die includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. Voltages are established for the plurality of electrically-isolated test structures. These voltages are different than the voltages of the plurality of non-electrically-isolated test structures. A region of the semiconductor die is continuously inspected in a first direction thereby obtaining voltage contrast data indicative of whether there are defective test structures. The voltage contrast data is analyzed to determine whether there are one or more defective test structures.

Abstract: Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.

Abstract: Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element.

Abstract: Disclosed are methods and apparatus for simultaneously flooding a sample (e.g., a semiconductor wafer) to control charge and inspecting the sample. The apparatus includes a charged particle beam generator arranged to generate a charged particle beam substantially towards a first portion of the sample and a flood gun for generating a second beam towards a second portion of the sample. The second beam is generated substantially simultaneously with the inspection beam. The apparatus further includes a detector arranged to detect charged particles originating from the sample portion. In a further implementation, the apparatus further includes an image generator for generating an image of the first portion of the sample from the detected particles. In one embodiment, the sample is a semiconductor wafer. In a method aspect, a first area of a sample is flooded with a flood beam to control charge on a surface of the sample. A second area of the sample is inspected with an inspection beam.

Abstract: Disclosed is a method of inspecting a sample. The sample is illuminated with an incident beam, thereby causing voltage contrast within structures present on the sample. Voltage contrast is detected within the structures. Information from the detected voltage contrast is stored, and position data concerning the location of features corresponding to at least a portion of the stored voltage contrast information is also stored. In a specific embodiment, the features represent electrical defects present on the sample. In another embodiment, the stored position data is in the form of a two dimensional map. In another aspect, the sample is re-inspected and the stored position data is used in analyzing data resulting from the re-inspection.

Abstract: A system and method for controlling electron exposure on image specimens by adjusting a raster scan area in-between scan frame cycles. A small, zoomed-in, scan area and the surrounding area are flooded with positive charge for a number of frame cycles between scan frames to reduce the voltage differential between the scan area and surrounding area, thereby reducing the positive charge buildup which tends to obscure small features in scanned images. The peak current into a pixel element on the specimen is reduced by scanning the beam with a line period that is very short compared to regular video. Frames of image data may further be acquired non-sequentially, in arbitrarily programmable patterns. Alternatively, an inert gas can be injected into the scanning electron microscope at the point where the electron beam impinges the specimen to neutralize a charge build-up on the specimen by the ionization of the inert gas by the electron beam.

Abstract: A system and method for controlling electron exposure on image specimens by adjusting a raster scan area in-between scan frame cycles. A small, zoomed-in, scan area and the surrounding area are flooded with positive charge for a number of frame cycles between scan frames to reduce the voltage differential between the scan area and surrounding area, thereby reducing the positive charge buildup which tends to obscure small features in scanned images. The peak current into a pixel element on the specimen is reduced by scanning the beam with a line period that is very short compared to regular video. Frames of image data may further be acquired non-sequentially, in arbitrarily programmable patterns. Alternatively, an inert gas can be injected into the scanning electron microscope at the point where the electron beam impinges the specimen to neutralize a charge build-up on the specimen by the ionization of the inert gas by the electron beam.

Abstract: A cDNA sequence encoding human T11 or a fragment thereof which is capable of inhibiting T-lymphocyte activation.

Abstract: A cDNA sequence encoding human T11 or a fragment thereof which is capable of inhibiting T-lymphocyte activation.

Abstract: A cDNA sequence encoding human T11 or a fragment thereof which is capable of inhibiting T-lymphocyte activation.

Abstract: An electron-beam test probe system (400) in which a pulsed laser-beam source (404) and a photocathode assembly (430) are used with an electron-beam column (426) to produce a pulsed electron beam at a stabilized repetition frequency. A pulse picker (414) allows the pulse repetition frequency of the pulsed electron beam to be reduced to a submultiple of the pulsed laser repetition frequency. A test pattern generator (416) is programmable to apply a desired pattern of test vector patterns to an electronic circuit to be probed, the test vector patterns being synchronized with the stabilized laser-beam pulse repetition frequency. A timebase circuit (412) allows the test vector patterns to be time-shifted relative to the pulsed electron beam. The electronic circuit under test can thus be probed at any desired point in the applied test vector pattern by control of the pulse picker and by time-shifting the test vector pattern.

Abstract: A surface is probed with a pulsed electron beam and secondary electrons are detected to produce a detector signal. First portions of the detector signal are substantially dependent on the voltage of the surface being probed, while second portions of the detector signal are substantially independent of the voltage of the surface being probed. In general, the first and second portions of the detector signal include unwanted noise caused by low-level sampling due to beam leakage and/or by scintillator afterglow in the secondary-electron detector. The detector signal is sampled during the first signal portions and is sampled during the second signal portions. The sampled first signal portions are combined with the complement of the sampled second signal portions to produce a measured voltage signal representing voltage of the conductor. In a preferred sampling scheme, alternate electron-beam sampling pulses are held-off.

Abstract: Methods and apparatus are disclosed for conditional acquisition of potential measurements in integrated circuits, with the aid of electron-beam probes. The conditional acquisition enables display of waveform images which permit diagnosis of the causes and/or origins of failure in circuits which fail intermittently. Data is acquired in the normal manner on each pass through the test pattern. At the end of each test pattern execution a pass/fail signal from the tester exercising the circuit is used to reject or accept the acquired data. In this fashion, it is possible to accumulate only that data which carries information about the failure of interest and to reject data which does not. Over several test pattern repetitions it is possible to display only that data which shows the failure. Engineers are thus able to efficiently diagnose intermittent failures without the need to change device operating parameters.

Abstract: Apparatus is provided which includes a FIB column having a vacuum chamber for receiving an IC, means for applying a FIB to the IC, means for detecting secondary charged particles emitted as the FIB is applied to the IC, and means for electrically stimulating the IC as the FIB is applied to the IC. The apparatus may be used, for example, (1) to locate a conductor buried under dielectric material within the IC, (2) for determining milling end-point when using the FIB to expose a buried conductor of the IC, and (3) to verify the repair of an IC step-by-step as the repair is made.

Abstract: A magnetic lens for use in an electron beam test probe system which includes an electron beam which travels along an electron beam column axis to reach the surface of a specimen which is to be examined. The magnetic lens focuses the electron beam to a selected point on the surface of the specimen. This magnetic lens also collects and collimates the secondary electrons produced in response to the electron beam bombardment of the specimen. The magnetic lens includes deflection coils for selecting the point on the specimen surface at which the electron beam is focused. The magnetic lens generates a magnetic field having a first region of intense magnetic flux substantially coincident with the selected point on the specimen surface and a second region of lesser uniform magnetic flux in which the magnetic flux lines are parallel to the electron beam column axis. This field is generated by the combination of a stationary magnetic field and a deflection magnetic field.

Abstract: An improved electron beam test probe apparatus and a method for use of said apparatus for use in measuring the potential in a specimen which enables measurements to be insensitive to local electric fields in the vicinity of the point at which the potential of the specimen is being measured. The apparatus consists of an electron beam for bombarding the specimen at the point at which the potential of the specimen is to be measured, a magnetic lens for collimating the secondary electrons emitted fom the specimen in response to this bombardment, and a detector system for measuring the energy distribution of the secondary electrons so collimated. Tubular electrodes are employed in the energy distribution detection system. These electrodes have significantly higher field uniformity and intercept a smaller fraction of the secondary electrons than wire mesh electrodes.

Abstract: An apparatus for pulsing an electron beam in an electron beam test probe used for examining integrated circuits is disclosed. The apparatus includes a structure having two intersecting channels cut therein. The electron beam passes through a first one of these channels enroute to the integrated circuit being tested. A linear conductor is disposed along the axis of the second channel such that the combination of said conductor and said second channel forms a coaxial transmission line. An electric field is generated in the second channel by applying a suitable potential between the linear conductor and the second channel. This electric field extends into the first channel from the region common to both channels.

Abstract: An electron beam test probe system for analyzing the operation of an integrated circuit is described. It includes a circuit for generating a test signal pattern and coupling the test signal pattern to the integrated circuit under test. It also includes an electron beam test probe for making potential measurements at specified points on the surface of the integrated circuit. These potential measurements can be displayed as an image of the surface of the integrated circuit or as a graph of the potential at a specified point on the surface of the integrated circuit as a function of time for times chosen with respect to the test signal pattern. The points at which potential measurements are made may be specified with reference to a schematic diagram of the integrated circuit. The schematic diagram may be inputted to the test probe system in a format which is consistent with that used by currently available circuit simulation programs.