Abstract: An oscillator circuit comprising first and second resonator terminals for connecting to respective terminals of a resonator. The oscillator circuit also comprises a first inverting amplifier connected between the first and second resonator terminals in a first mode of operation; and a back to back pair of second inverting amplifiers connected between the first and second resonator terminals in a second mode of operation. There is also provided a controller configured to compare an operational parameter of the oscillator circuit to a switchover threshold, and switch the oscillator circuit from the first mode of operation to the second mode of operation when the operational parameter exceeds the switchover threshold.

Abstract: The present invention relates to a polar signal generator and method of deriving phase and amplitude components from in-phase (I) and quadrature-phase (Q) components of an input signal, wherein the I and Q components are generated at a first sampling frequency based on the input signal, and are then up-sampled in accordance with a predetermined first interpolation factor (N), to generate up-sampled I and Q components at a second sampling frequency higher than the first sampling frequency. The up-sampled I and Q components are converted into the phase and amplitude components, wherein the converting step is operated at the second sampling frequency. Moreover, the phase and amplitude components can be further up-sampled, optionally by different sampling frequencies, to a third and a fourth sampling frequency. Thereby, I-Q generation and cartesian-to-polar transformation can be performed at lower frequencies, which reduces power consumption.

Abstract: The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).

Abstract: The present application relates to at least one digitally controlled oscillator and a data modulation device. More particularly, the digital polar transmitter comprises at least one digitally controlled oscillator configured to generate at least one frequency. The digital polar transmitter comprises a data modulation device, wherein the data modulation device comprises at least one data input terminal, at least one output terminal, and at least one frequency input terminal, wherein the output terminal is connected to the digitally controlled oscillator. The digital polar transmitter comprises a phase measuring device configured to measure phase information from the output signal of the data modulation device for every frequency sample.

Abstract: An x-ray system having a C-arm 1 and an associated method are provided. The x-ray system includes at least one adjustment unit for at least one component of the x-ray system that is actively connected to the C-arm. The at least one adjustment unit compensates for a spatial change in position of the component caused by deformation and/or oscillation of the C-arm.

Abstract: A portable electronic device for exchanging encrypted data with other electronic devices includes a processor, a memory operatively coupled to the processor, and a prime number generation circuit operatively coupled to the processor and memory. The prime number generation circuit includes logic that generates at least two prime numbers based on unique data stored in the electronic device, wherein said at least two prime numbers are always the same at least two prime numbers. The generated prime numbers then can be used to generate RSA public and private keys within the electronic device.

Abstract: A hydrogen generator for producing hydrogen and oxygen gases comprising a housing having an electrolyte reservoir and an electrolysis cell, an electrical power source; a plurality of axially spaced-apart alternating positive and negative electrode plates mounted concentrically and separated from each other by a peripheral sealing ring in the electrolysis chamber; a pair of opposite tabs formed on the perimeter of the plates with openings for receiving an electrode support rod therein, positive electrode plates connected to a positive electrode support rod and negative electrode plates connected to a negative electrode support rod for electrically connecting the positive and the negative electrode plates to the power source, and fluid conduits for conveying liquid electrolyte from the reservoir to the electrolysis cell and for conveying hydrogen and oxygen gases from the electrolysis chamber; the electrode plates comprise a titanium plate having a 1-3 micron platinum coating, said plates preferably having a ci

Abstract: Calibration data for calibrating time to digital conversion is obtained by switching a feed circuit of a time to digital converter between a normal operating mode or a calibration mode. A delay circuit with a delay circuit input and a plurality of taps outputs. A sampling register samples data from the data inputs. The feed circuit provides for selection of transitions of the oscillator signal that control timing of a first active transition at the clock circuit after a transition at the delay circuit input. A control circuit switches the feed circuit between normal operating mode and calibration mode, and controls the feed circuit successively to select a plurality of different transitions to control timing of the first active transition in the calibration mode. The control circuit reads out resulting data from the sampling register for each selection and determines calibration data for the oscillator signal from said data.

Abstract: A digital phase locked loop (300) configured to receive a reference clock signal (302) and a channel control word (308), and to generate an output clock signal (304). The digital phase locked loop comprising an adjustable delay component (306) configured to: receive the reference clock signal (302), apply a time delay to the reference clock signal (302) in accordance with a time delay control signal (316); and provide a delayed reference clock signal (318).

Abstract: An output stage (1) for a digital RF transmitter is provided. The output stage comprises: an input adapted to receive an input signal (RFin, b7-b0) to be transmitted; a plurality N of power amplification sections (S1, S2, S3, S4); and an output (A, B) providing an output voltage signal. Each of the N power amplification sections (S1, S2, S3, S4) is arranged to receive the input signal (RFin, b7-b0) and comprises a transformer (T1, T2, T3, T4) adapted to provide a respective output signal. Each transformer comprises a primary stage and a secondary stage; the secondary stages of the transformers (T1, T2, T3, T4) of the N power amplification sections (S1, S2, S3, S4) are combined such that a combined output voltage signal of the output stage is provided. The N power amplification sections (S1, S2, S3, S4) are adapted such that the input signal (RFin, b7-b0) is latched by clock signals (clock1, clock2, clock3, clock4) comprising different phases.

Abstract: The present application relates to a digital modulator comprising an output stage comprising a number of unit cell arrays, and a sampling stage. The present application relates also to a communication device comprising said digital modulator, a method for digitally modulating and a computer program product. More particularly, the digital modulator comprises an output stage comprising a number of unit cell arrays, wherein the output stage comprises at least one carrier frequency signal input terminal configured to receive a carrier frequency signal. The digital modulator comprises a sampling stage connectable to the output stage, wherein the sampling stage is configured to oversample at least one data input signal. The digital modulator comprises at least one sampling clock generating device configured to generate at least one sampling clock signal depending on the number of arranged unit cell arrays and the carrier frequency signal.

Abstract: Calibration data for calibrating time to digital conversion is obtained by switching a feed circuit (20) of a time to digital converter between a normal operating mode or a calibration mode. A delay circuit (22) with a delay circuit input and a plurality of taps outputs respective, differently delayed versions of a signal from a delay circuit input. A sampling register (24) has data inputs coupled to the taps, and samples data from the data inputs in response to an active transition at a clock input. When in the normal operating mode, the feed circuit (2) feeds an oscillator signal of an oscillator circuit (10) to the delay circuit input and a reference signal to the clock input of the sampling register (24). When in the calibration mode, the feed circuit (20) supplies signals with transitions having timing controlled by the oscillator signal to both the delay circuit input and the clock input.

Abstract: The invention relates to frequency conversion systems, in particular for use as up-converters or down-converters in radiofrequency (RF) receivers or transmitters, exemplary embodiments including a radiofrequency receiver (1000) comprising: an RF signal input (1001); a mixing module (1002) comprising a first plurality of IF amplifiers (10041-3) each connected to the RF signal input (1001) via a switch (10031-3); a multi-phase local oscillator signal generator (1300) configured to provide a switching signal to each switch (10031-3); and a summing module (1005) configured to receive output signals from each of the IF amplifiers (10041-3) and to provide a second plurality of output IF signals from a weighted sum of the IF amplifier output signals, wherein the second plurality is different to the first plurality.

Abstract: The present invention relates to a polar transmission method and a polar transmitter for transmitting phase and amplitude components derived from in-phase (I) and quadrature-phase (Q) components of an input signal. A first conversion is provided for converting the in-phase (I) and quadrature-phase (Q) components into the phase and amplitude components at a first sampling rate. Additionally, a second conversion is provided for converting the phase component into a frequency component, wherein the second conversion comprises a rate conversion for converting the first sampling rate into a lower second sampling rate at which the frequency component is provided. Thereby, the second sampling rate can be used as a lower update rate in a digitally controlled oscillator in order to save power or because of speed limitations, while the surplus phase samples obtain due to the higher first sampling rate enable better approximation of the phase component after the digitally controlled oscillator.

Abstract: The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).

Abstract: The present application relates to a digital modulator comprising an output stage comprising a number of unit cell arrays, and a sampling stage. The present application relates also to a communication device comprising said digital modulator, a method for digitally modulating and a computer program product. More particularly, the digital modulator comprises an output stage comprising a number of unit cell arrays, wherein the output stage comprises at least one carrier frequency signal input terminal configured to receive a carrier frequency signal. The digital modulator comprises a sampling stage connectable to the output stage, wherein the sampling stage is configured to oversample at least one data input signal. The digital modulator comprises at least one sampling clock generating device configured to generate at least one sampling clock signal depending on the number of arranged unit cell arrays and the carrier frequency signal.

Abstract: A tuning method and tuner apparatus having a plurality of frequency conversion stages for concurrently receiving more than one channel. To avoid disturbance by oscillator pulling, a multi-phased local oscillator signal required by sub-mixers of a DAC mixer share the same timing reference. To minimize the complexity, die area and power dissipation of the local oscillation generation, a tuning offset is accepted from each of the down-conversion stages, and loss of receiver performance by the tuning offset is avoided by a control function for controlling the receiver circuit to process an increased dynamic range introduced by the tuning offset.

Abstract: The present application relates to at least one digitally controlled oscillator and a data modulation device. More particularly, the digital polar transmitter comprises at least one digitally controlled oscillator configured to generate at least one frequency. The digital polar transmitter comprises a data modulation device, wherein the data modulation device comprises at least one data input terminal, at least one output terminal, and at least one frequency input terminal, wherein the output terminal is connected to the digitally controlled oscillator. The digital polar transmitter comprises a phase measuring device configured to measure phase information from the output signal of the data modulation device for every frequency sample.

Abstract: A digital phase locked loop (300) configured to receive a reference clock signal (302) and a channel control word (308), and to generate an output clock signal (304). The digital phase locked loop comprising an adjustable delay component (306) configured to: receive the reference clock signal (302), apply a time delay to the reference clock signal (302) in accordance with a time delay control signal (316); and provide a delayed reference clock signal (318).

Abstract: An output stage (1) for a digital RF transmitter is provided. The output stage comprises: an input adapted to receive an input signal (RFin, b7-b0) to be transmitted; a plurality N of power amplification sections (S1, S2, S3, S4); and an output (A, B) providing an output voltage signal. Each of the N power amplification sections (S1, S2, S3, S4) is arranged to receive the input signal (RFin, b7-b0) and comprises a transformer (T1, T2, T3, T4) adapted to provide a respective output signal. Each transformer comprises a primary stage and a secondary stage; the secondary stages of the transformers (T1, T2, T3, T4) of the N power amplification sections (S1, S2, S3, S4) are combined such that a combined output voltage signal of the output stage is provided. The N power amplification sections (S1, S2, S3, S4) are adapted such that the input signal (RFin, b7-b0) is latched by clock signals (clock1, clock2, clock3, clock4) comprising different phases.