Abstract: A memory card reading method applied to an electronic device, includes: detecting a specification information of a memory card, wherein the specification information includes a transfer speed of the memory; and controlling according to the specification information a reader to host interface to operate in a first operating mode or a second operating mode for reading the memory card, wherein the first operating mode and the second operating mode correspond to different data transfer speeds.

Abstract: The present invention discloses an intermediate circuit including: a detection circuit generating a detection result indicating a memory card signal conforming to one of a first and a second voltage specifications which specify a higher first operation voltage and a lower second operation voltage respectively; a control circuit generating a conversion control signal and a selection control signal according to the detection result; a conversion circuit converting the memory card signal into a card-to-system conversion signal conforming to the second voltage specification according to the conversion control signal when the memory card signal conforms to the first voltage specification; and a selection circuit outputting the card-to-system conversion signal according to the selection control signal when the memory card signal conforms to the first voltage specification, and outputting the memory card signal according to the selection control signal when the memory card signal conforms to the second voltage speci

Abstract: An SSIC (SuperSpeed Inter-Chip) device comprises a detecting circuit operable to execute at least one of a first and a second detection processes and generate a detection result, wherein the first detection process is operable to detect an SSIC compatible object and the second detection process is operable to detect whether the SSIC compatible object satisfies at least one of a de-link state and a re-link state, a control circuit operable to generate a control signal according to the detection result, and a Mobile-Physical-Layer circuit operable to execute at least one of the following steps: if the control signal indicates that the SSIC compatible object is detected and satisfies the de-link state, disconnecting a normal connection between the SSIC device and the SSIC host; and if the control signal indicates that the SSIC compatible object is detected and satisfies the re-link state, connecting the SSIC device with the SSIC host.

Abstract: A USB control circuit of a USB hub device includes: an upstream MAC-layer circuit; a downstream MAC-layer circuit; a first USB PHY-layer circuit; a second USB PHY-layer circuit; a first switch circuit for communicating data with an upstream port through the first USB PHY-layer circuit; a second switch circuit for communicating data with a downstream port through the second USB PHY-layer circuit; a control signal transmission interface; a signal repeater circuit; and a control unit configured to operably control the first switch circuit and the second switch circuit through the control signal transmission interface, so that the first switch circuit selectively couples the upstream MAC-layer circuit or the signal repeater circuit with the first USB PHY-layer circuit, while the second switch circuit selectively couples the downstream MAC-layer circuit or the signal repeater circuit with the second USB PHY-layer circuit.

Abstract: This invention discloses a memory card access module and a memory card access method. The memory card access method is applied to an electronic device. A processing unit of the electronic device accesses a memory card through a memory card slot. The method includes steps of: detecting whether the memory card supports a Peripheral Component Interconnect Express (PCIe) interface; when the memory card does not support the PCIe interface, controlling the processing unit to access the memory card through a first data transmission path and performing data format conversion between a transmission interface and the PCIe interface using a memory card access unit disposed on the first data transmission path; and when the memory card supports the PCIe interface, controlling the processing unit to access the memory card through a second data transmission path that allows the processing unit and the memory card to transmit data through the PCIe interface.

Abstract: A USB hub device includes an upstream port and a downstream port. A USB control circuit of the USB control circuit includes an upstream interface; a downstream interface; a first switch circuit for coupling with the upstream port; a second switch circuit for coupling with the downstream port; a control signal transmission interface coupled with the first switch circuit and the second switch circuit; and a control unit, coupled with the control signal transmission interface, configured to operably control the first switch circuit and the second switch circuit through the control signal transmission interface, so that the first switch circuit selectively couples one of the upstream interface and the second switch circuit with the upstream port, while the second switch circuit selectively couples one of the downstream interface and the first switch circuit with the downstream port.

Abstract: The present invention discloses an intermediate circuit including: a detection circuit generating a detection result indicating a memory card signal conforming to one of a first and a second voltage specifications which specify a higher first operation voltage and a lower second operation voltage respectively; a control circuit generating a conversion control signal and a selection control signal according to the detection result; a conversion circuit converting the memory card signal into a card-to-system conversion signal conforming to the second voltage specification according to the conversion control signal when the memory card signal conforms to the first voltage specification; and a selection circuit outputting the card-to-system conversion signal according to the selection control signal when the memory card signal conforms to the first voltage specification, and outputting the memory card signal according to the selection control signal when the memory card signal conforms to the second voltage speci

Abstract: The present invention discloses an intermediate circuit including: a detection circuit detecting a memory card signal to generate a detection result indicating the memory card signal conforming to one of a first and a second signal types which are dedicated to different physical transmission interfaces respectively; a control circuit generating a conversion control signal and a selection control signal according to the detection result; a conversion circuit converting the memory card signal into a card-to-system conversion signal of the second signal type according to the conversion control signal when the memory card signal conforms to the first signal type; and a selection circuit outputting the card-to-system conversion signal according to the selection control signal when the memory card signal conforms to the first signal type, and outputting the memory card signal according to the selection control signal when the memory card signal conforms to the second signal type.

Abstract: A memory card reading method applied to an electronic device, includes: detecting a specification information of a memory card, wherein the specification information includes a transfer speed of the memory; and controlling according to the specification information a reader to host interface to operate in a first operating mode or a second operating mode for reading the memory card, wherein the first operating mode and the second operating mode correspond to different data transfer speeds.

Abstract: A hub hub control method, wherein the hub possesses an uplink port and a plurality of downlink ports, includes: receiving link status of each downlink port to know whether each downlink port has built a link; and when none of the plurality of downlink ports has built a link, controlling the uplink port to be unable to build a link. A hub control circuit, the hub possessing an uplink port and a plurality of downlink ports, includes a link status reception unit and an uplink port control unit for respective execution of the two steps of the hub control method.

Abstract: A USB hub device includes an upstream port and a downstream port. A USB control circuit of the USB control circuit includes an upstream interface; a downstream interface; a first switch circuit for coupling with the upstream port; a second switch circuit for coupling with the downstream port; a control signal transmission interface coupled with the first switch circuit and the second switch circuit; and a control unit, coupled with the control signal transmission interface, configured to operably control the first switch circuit and the second switch circuit through the control signal transmission interface, so that the first switch circuit selectively couples one of the upstream interface and the second switch circuit with the upstream port, while the second switch circuit selectively couples one of the downstream interface and the first switch circuit with the downstream port.

Abstract: A USB control circuit of a USB hub device includes: an upstream MAC-layer circuit; a downstream MAC-layer circuit; a first USB PHY-layer circuit; a second USB PHY-layer circuit; a first switch circuit for communicating data with an upstream port through the first USB PHY-layer circuit; a second switch circuit for communicating data with a downstream port through the second USB PHY-layer circuit; a control signal transmission interface; a signal repeater circuit; and a control unit configured to operably control the first switch circuit and the second switch circuit through the control signal transmission interface, so that the first switch circuit selectively couples the upstream MAC-layer circuit or the signal repeater circuit with the first USB PHY-layer circuit, while the second switch circuit selectively couples the downstream MAC-layer circuit or the signal repeater circuit with the second USB PHY-layer circuit.

Abstract: An SSIC (SuperSpeed Inter-Chip) device comprises a detecting circuit operable to execute at least one of a first and a second detection processes and generate a detection result, wherein the first detection process is operable to detect an SSIC compatible object and the second detection process is operable to detect whether the SSIC compatible object satisfies at least one of a de-link state and a re-link state, a control circuit operable to generate a control signal according to the detection result, and a Mobile-Physical-Layer circuit operable to execute at least one of the following steps: if the control signal indicates that the SSIC compatible object is detected and satisfies the de-link state, disconnecting a normal connection between the SSIC device and the SSIC host; and if the control signal indicates that the SSIC compatible object is detected and satisfies the re-link state, connecting the SSIC device with the SSIC host.

Abstract: A hub hub control method, wherein the hub possesses an uplink port and a plurality of downlink ports, includes: receiving link status of each downlink port to know whether each downlink port has built a link; and when none of the plurality of downlink ports has built a link, controlling the uplink port to be unable to build a link. A hub control circuit, the hub possessing an uplink port and a plurality of downlink ports, includes a link status reception unit and an uplink port control unit for respective execution of the two steps of the hub control method.

Abstract: A sampling phase calibrating method, comprising: transmitting a second command signal from a storage device controller, to read content in a storage device; transmitting a first command signal and a third data signal with a third sampling phase from the storage device controller to the storage device, according to the content; and determining if data transmitting from the storage device controller to the storage device has error, according to responding information that the storage device responds to the storage device controller corresponding to the first command signal and the third data signal, to determine if the third sampling phase is suitable; wherein the second command signal is transmitted via a second clock, the first command signal is transmitted via a first clock, where the second clock is slower than the first clock.