Patents by Inventor Nhat Nguyen
Nhat Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11038725Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.Type: GrantFiled: April 14, 2020Date of Patent: June 15, 2021Assignee: Rambus Inc.Inventors: Masum Hossain, Nhat Nguyen, Charles Walter Boecker
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Publication number: 20210152205Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.Type: ApplicationFiled: December 8, 2020Publication date: May 20, 2021Inventors: Masum HOSSAIN, Nhat NGUYEN, Yikui Jen DONG, Arash ZARGARAN-YAZD, Wendemagegnehu BEYENE
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Publication number: 20210050782Abstract: A switch-mode power supply circuit includes a low-side switching transistor, a high-side switching transistor, a low-side current sensing circuit, and a gate driver circuit. The low-side current sensing circuit is coupled to the low-side switching transistor and is configured to sense a current flowing through the low-side switching transistor. The gate driver circuit is coupled to the low-side current sensing circuit and the high-side switching transistor. The gate driver circuit is configured to generate a signal having a first drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being less than a threshold current, and to generate a signal having a second drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being greater than the threshold current. The first drive strength is greater than the second drive strength.Type: ApplicationFiled: April 28, 2020Publication date: February 18, 2021Inventors: Saurav Bandyopadhyay, Thomas Matthew LaBella, Huy Le Nhat Nguyen, Michael G. Amaro, Robert Allan Neidorff
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Patent number: 10892791Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.Type: GrantFiled: November 12, 2019Date of Patent: January 12, 2021Assignee: Rambus Inc.Inventors: Masum Hossain, Nhat Nguyen, Yikui Jen Dong, Arash Zargaran-Yazd, Wendemagegnehu Beyene
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Publication number: 20200366304Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: ApplicationFiled: May 28, 2020Publication date: November 19, 2020Inventors: Masum HOSSAIN, Kenneth C. DYER, Nhat NGUYEN, Shankar TANGIRALA
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Publication number: 20200313938Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.Type: ApplicationFiled: April 14, 2020Publication date: October 1, 2020Inventors: Masum Hossain, Nhat Nguyen, Charles Walter Boecker
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Patent number: 10734899Abstract: A system includes an input voltage supply and advanced current mode (ACM) converter device coupled to the input voltage supply. The ACM converter device (102) includes a pulse-skipping mode (PSM) transitions controller configured to switch between PSM and discontinuous conduction mode (DCM). The system also includes an output inductor coupled to a switch node of the ACM converter device. The system also includes an output capacitor with a first terminal coupled to the output inductor and a second terminal coupled to a ground node. The system also includes a voltage divider in parallel with the output capacitor, where the voltage divider is configured to provide a feedback voltage to the ACM converter device.Type: GrantFiled: January 28, 2019Date of Patent: August 4, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jiwei Fan, Mingyue Zhao, Huy Le Nhat Nguyen
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Patent number: 10707885Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: GrantFiled: February 11, 2019Date of Patent: July 7, 2020Assignee: Rambus Inc.Inventors: Masum Hossain, Kenneth C. Dyer, Nhat Nguyen, Shankar Tangirala
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Publication number: 20200212800Abstract: A system includes an input voltage supply and advanced current mode (ACM) converter device coupled to the input voltage supply. The ACM converter device (102) includes a pulse-skipping mode (PSM) transitions controller configured to switch between PSM and discontinuous conduction mode (DCM). The system also includes an output inductor coupled to a switch node of the ACM converter device. The system also includes an output capacitor with a first terminal coupled to the output inductor and a second terminal coupled to a ground node. The system also includes a voltage divider in parallel with the output capacitor, where the voltage divider is configured to provide a feedback voltage to the ACM converter device.Type: ApplicationFiled: January 28, 2019Publication date: July 2, 2020Inventors: Jiwei FAN, Mingyue ZHAO, Huy Le Nhat NGUYEN
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Publication number: 20200153468Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.Type: ApplicationFiled: November 12, 2019Publication date: May 14, 2020Inventors: Masum HOSSAIN, Nhat NGUYEN, Yikui Jen DONG, Arash ZARGARAN-YAZD, Wendemagegnehu BEYENE
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Patent number: 10637696Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.Type: GrantFiled: June 27, 2019Date of Patent: April 28, 2020Assignee: Rambus Inc.Inventors: Masum Hossain, Nhat Nguyen, Charles Walter Boecker
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Patent number: 10541609Abstract: In a power converter system, circuitry generates first and second PWM signals during a PWM cycle for controlling application of power to an inductor. Circuitry generates error signals having AC- and DC-components, the error signals being generated in response to indications of the power applied to or developed by the inductor. Circuitry generates a feedback control signal in response to the error signals. The first and second PWM signals are controlled in response to the feedback control signals.Type: GrantFiled: July 20, 2018Date of Patent: January 21, 2020Assignee: Texas Instruments IncorporatedInventors: Jiwei Fan, Mingyue Zhao, Huy Le Nhat Nguyen
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Publication number: 20200007363Abstract: A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.Type: ApplicationFiled: June 27, 2019Publication date: January 2, 2020Inventors: Masum Hossain, Nhat Nguyen, Charles Walter Boecker
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Patent number: 10516427Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.Type: GrantFiled: October 12, 2016Date of Patent: December 24, 2019Assignee: Rambus Inc.Inventors: Masum Hossain, Nhat Nguyen, Yikui Jen Dong, Arash Zargaran-Yazd, Wendemagegnehu Beyene
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Publication number: 20190245548Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: ApplicationFiled: February 11, 2019Publication date: August 8, 2019Inventors: Masum Hossain, Kenneth C. Dyer, Nhat Nguyen, Shankar Tangirala
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Patent number: 10348480Abstract: A receiver serial data streams generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the local clock to transitions in the data stream. This process is commonly known as clock and data recovery (CDR). Certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. Phase-error signals from multiple receivers receiving the multiple serial data streams are combined and used to make common phase adjustments to the frequency reference clock. These common adjustments track jitter that is common to the received data streams. Local adjustments that better align each respective local clock to the transitions of its respective serial data stream are made using a local phase-error signal. These local adjustments track jitter that is more unique to each of the respective serial data streams.Type: GrantFiled: October 31, 2017Date of Patent: July 9, 2019Assignee: Rambus Inc.Inventors: Masum Hossain, Nhat Nguyen, Yikui Jen Dong, Arash Zargaran-Yazd
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Patent number: 10230384Abstract: A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.Type: GrantFiled: November 20, 2017Date of Patent: March 12, 2019Assignee: Rambus Inc.Inventors: Masum Hossain, Kenneth C. Dyer, Nhat Nguyen, Shankar Tangirala
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Publication number: 20180351455Abstract: In a power converter system, circuitry generates first and second PWM signals during a PWM cycle for controlling application of power to an inductor. Circuitry generates error signals having AC- and DC-components, the error signals being generated in response to indications of the power applied to or developed by the inductor. Circuitry generates a feedback control signal in response to the error signals. The first and second PWM signals are controlled in response to the feedback control signals.Type: ApplicationFiled: July 20, 2018Publication date: December 6, 2018Inventors: Jiwei Fan, Mingyue Zhao, Huy Le Nhat Nguyen
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Publication number: 20180248577Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.Type: ApplicationFiled: October 12, 2016Publication date: August 30, 2018Inventors: Masum HOSSAIN, Nhat NGUYEN, Yikui Jen DONG, Arash ZARGARAN-YAZD, Wendemagegnehu BEYENE
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Publication number: 20180248479Abstract: In a power converter system, circuitry generates first and second PWM signals during a PWM cycle for controlling application of power to an inductor. Circuitry generates error signals having AC- and DC-components, the error signals being generated in response to indications of the power applied to or developed by the inductor. Circuitry generates a feedback control signal in response to the error signals. The first and second PWM signals are controlled in response to the feedback control signals.Type: ApplicationFiled: October 5, 2017Publication date: August 30, 2018Inventors: Jiwei Fan, Mingyue Zhao, Huy Le Nhat Nguyen