Patents by Inventor Niamh Waldron
Niamh Waldron has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11646200Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.Type: GrantFiled: May 18, 2021Date of Patent: May 9, 2023Assignee: IMEC VZWInventors: Liesbeth Witters, Niamh Waldron, Amey Mahadev Walke, Bernardette Kunert, Yves Mols
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Patent number: 11322390Abstract: The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate.Type: GrantFiled: April 9, 2020Date of Patent: May 3, 2022Assignee: IMEC vzwInventors: Amey Mahadev Walke, Niamh Waldron, Nadine Collaert, Ming Zhao
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Patent number: 11195767Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.Type: GrantFiled: August 23, 2019Date of Patent: December 7, 2021Assignee: IMEC VZWInventors: Amey Mahadev Walke, Liesbeth Witters, Niamh Waldron, Robert Langer, Bernardette Kunert
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Publication number: 20210358748Abstract: A method for forming a III-V construction over a group IV substrate comprises providing an assembly comprising the group IV substrate and a dielectric thereon. The dielectric layer comprises a trench exposing the group IV substrate. The method further comprises initiating growth of a first III-V structure in the trench, continuing growth out of the trench on top of the bottom part, growing epitaxially a sacrificial second III-V structure on the top part of the first III-V structure, and growing epitaxially a third III-V structure on the sacrificial second III-V structure. The third III-V structure comprises a top III-V layer. The method further comprises physically disconnecting a first part of the top layer from a second part thereof, and contacting the sacrificial second III-V structure with the liquid etching medium.Type: ApplicationFiled: May 18, 2021Publication date: November 18, 2021Inventors: Liesbeth Witters, Niamh Waldron, Amey Mahadev Walke, Bernardette Kunert, Yves Mols
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Publication number: 20210151593Abstract: A method comprising: providing a semiconductor structure including: a channel, a barrier, a non-conductive structure over the barrier, the non-conductive structure including a cavity having sidewalls separated by a first distance, providing a first non-conductive layer conformally over the non-conductive structure, thereby covering the sidewalls and the bottom surface of the cavity, etching the first non-conductive layer in such a way that it is removed from at least part of the bottom surface but still covers the sidewalls, etching through the bottom surface at most until the channel is reached, by using the first non-conductive layer covering the sidewalls as a mask, thereby forming an opening in the bottom surface of the non-conductive structure, the opening having sidewalls separated by a second distance, smaller than the first distance, and completely removing the first non-conductive layer.Type: ApplicationFiled: November 17, 2020Publication date: May 20, 2021Inventors: Niamh Waldron, AliReza Alian, Uthayasankaran Peralagu
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Patent number: 11004962Abstract: The disclosed technology generally relates to integrated circuit devices having at least one transistor, and methods of fabricating the same. In one aspect, an integrated circuit device can be produced from a silicon substrate and can include at least one nano-ridge transistor formed from III-V semiconducting crystal portions. The III-V portions can be grown epitaxially from the silicon substrate using an intermediate portion which can be adapted to produce aspect ratio trapping. The nano-ridge transistor can have a reduced footprint on the silicon substrate, may be adapted for power RF applications, and can be combined with MOS or CMOS transistors within one and a same integrated circuit.Type: GrantFiled: August 27, 2019Date of Patent: May 11, 2021Assignee: IMEC vzwInventors: Robert Langer, Niamh Waldron, Bernardette Kunert
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Publication number: 20200328108Abstract: The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate.Type: ApplicationFiled: April 9, 2020Publication date: October 15, 2020Inventors: Amey Mahadev Walke, Niamh Waldron, Nadine Collaert, Ming Zhao
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Publication number: 20200091003Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.Type: ApplicationFiled: August 23, 2019Publication date: March 19, 2020Inventors: Amey Mahadev Walke, Liesbeth Witters, Niamh Waldron, Robert Langer, Bernardette Kunert
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Publication number: 20200075750Abstract: The disclosed technology generally relates to integrated circuit devices having at least one transistor, and methods of fabricating the same. In one aspect, an integrated circuit device can be produced from a silicon substrate and can include at least one nano-ridge transistor formed from III-V semiconducting crystal portions. The III-V portions can be grown epitaxially from the silicon substrate using an intermediate portion which can be adapted to produce aspect ratio trapping. The nano-ridge transistor can have a reduced footprint on the silicon substrate, may be adapted for power RF applications, and can be combined with MOS or CMOS transistors within one and a same integrated circuit.Type: ApplicationFiled: August 27, 2019Publication date: March 5, 2020Inventors: Robert Langer, Niamh Waldron, Bernardette Kunert
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Patent number: 10566250Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.Type: GrantFiled: February 8, 2019Date of Patent: February 18, 2020Assignee: IMEC vzwInventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
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Publication number: 20190244862Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.Type: ApplicationFiled: February 8, 2019Publication date: August 8, 2019Inventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
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Patent number: 10340188Abstract: The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group IV, a group III-IV or a group II-VI semiconductor material, to a handling wafer. The method includes forming the active layer on a sacrificial layer of the donor wafer, bonding the donor wafer to the handling wafer, and selectively etching the sacrificial layer to remove the donor wafer from the handling wafer, thereby leaving the active layer on the handling wafer.Type: GrantFiled: August 25, 2017Date of Patent: July 2, 2019Assignee: IMEC vzwInventors: Yves Mols, Niamh Waldron, Bernardette Kunert
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Patent number: 10224250Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.Type: GrantFiled: September 22, 2017Date of Patent: March 5, 2019Assignee: IMEC vzwInventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
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Publication number: 20180082901Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.Type: ApplicationFiled: September 22, 2017Publication date: March 22, 2018Inventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
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Publication number: 20180061712Abstract: The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group IV, a group III-IV or a group II-VI semiconductor material, to a handling wafer. The method includes forming the active layer on a sacrificial layer of the donor wafer, bonding the donor wafer to the handling wafer, and selectively etching the sacrificial layer to remove the donor wafer from the handling wafer, thereby leaving the active layer on the handling wafer.Type: ApplicationFiled: August 25, 2017Publication date: March 1, 2018Inventors: Yves Mols, Niamh Waldron, Bernardette Kunert
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Patent number: 9601488Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.Type: GrantFiled: April 25, 2016Date of Patent: March 21, 2017Assignee: IMEC VZWInventors: Niamh Waldron, Clement Merckling, Nadine Collaert
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Publication number: 20160240532Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.Type: ApplicationFiled: April 25, 2016Publication date: August 18, 2016Inventors: Niamh Waldron, Clement Merckling, Nadine Collaert
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Patent number: 9355889Abstract: The disclosed technology generally relates to semiconductor-on-insulator (SOI) devices and more particularly to SOI devices having a channel region comprising a Group III-V or a Group IV semiconductor material, and also relates to methods of fabricating the same. In one aspect, a method comprises providing a pre-patterned donor wafer, providing a handling wafer and bonding the pre-patterned donor wafer to the handling wafer by contacting the first oxide layer to the handling wafer. Providing a pre-patterned donor wafer comprises providing a donor substrate comprising a first semiconductor material, forming shallow trench isolation (STI) regions in the donor substrate, and forming fins in the donor substrate in between the STI regions, where each fin comprises a Group III-V or Group IV semiconductor material that is different from the first semiconducting material and laterally extends in a direction parallel to a major surface of the donor substrate and between the STI regions.Type: GrantFiled: March 30, 2015Date of Patent: May 31, 2016Assignee: IMEC VZWInventor: Niamh Waldron
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Patent number: 9324818Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.Type: GrantFiled: March 27, 2015Date of Patent: April 26, 2016Assignee: IMEC VZWInventors: Niamh Waldron, Clement Merckling, Nadine Collaert
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Patent number: 9218964Abstract: Methods of manufacturing a III-V compound semiconductor material, and the semiconductor material thus manufactured, are disclosed. In one embodiment, the method comprises providing a substrate comprising a first semiconductor material having a {001} orientation and an insulating layer overlaying the first semiconductor material. The insulating layer comprises a recessed region exposing an exposed region of the first semiconductor material. The method further comprises forming a buffer layer overlaying the exposed region that comprises a group IV semiconductor material. The method further comprises thermally annealing the substrate and the buffer layer, thereby roughening the buffer layer to create a rounded, double-stepped surface having a step density and a step height. A product of the step density and the step height is greater than or equal to 0.05 on the surface.Type: GrantFiled: August 5, 2011Date of Patent: December 22, 2015Assignees: IMEC, Katholieke Universiteit Leuven, KU Leuven R&DInventors: Gang Wang, Matty Caymax, Maarten Leys, Wei-e Wang, Niamh Waldron