Abstract: A semiconductor structure including a device layer, a back end-of-line layer, and a backside power distribution layer. The backside power distribution layer includes a first line network with having a first pitch, and a second line network having a second pitch. The second pitch is greater than the first pitch. In one example, the second pitch is at least 7 times (7×) greater than the first pitch.

Abstract: A microelectronic structure including a backside-power-distribution-network (BSDPN) connected to a backside of a device region. The BSPDN includes a plurality of first type power rails and a plurality of second type power rails located on the same level. A first power plane located on a level above the plurality of first type power rails and the plurality of second type power rails. The first power plane extends across the plurality of first type power rails and the plurality of second type power rails and the first power plane is connected to a plurality of first type power rails, but not connected to the plurality of second type power rails.

Abstract: A semiconductor structure includes a stacked device structure containing a first device and a second device over the first device in a stacked configuration. The semiconductor structure further includes a first backside contact connected to the first device and a first backside power line. The semiconductor structure further includes a second backside contact connected to the second device and a second backside power line.

Abstract: A semiconductor structure includes a plurality of vertical transport field effect transistors, and an interconnect structure connected to one of respective source/drain regions of at least two vertical transport field effect transistors of the plurality of vertical transport field effect transistors and respective gate regions of the at least two vertical transport field effect transistors. The interconnect structure comprises a damascene portion, and a subtractive portion disposed on the damascene portion.

Abstract: A semiconductor structure with a first backside metal level that has a plurality of first type of lines and at least one second type line. The first type of lines have a wider top surface than the bottom surface and have a first width. The first type of lines each connect by a first via to a second backside metal level. Each of first type of lines and the second type line connect by a second via to a through-silicon via. The second type line is narrower than the first type of lines. Each of the second type line is between adjacent first type of lines. The second type line has a top surface that is in the middle of the first type of lines, below the first type of lines, above, or level with the top surface of the first type of lines.

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a subtractively formed via located on top of a lower level metal line. The subtractively formed via has a bottom portion and a top portion. The semiconductor interconnect structure further includes a selectively grown region formed onto the top portion of the subtractively formed via. A portion of the selectively grown region overhangs the bottom portion of the subtractively formed via in one or more directions.

Abstract: According to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. The second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. A first backside signal line and a second backside signal line are located at a cell boundary of the first nanodevice. A first gap exists between the first backside signal line and the second backside signal line.

Abstract: A semiconductor structure includes a stacked device structure having a first field-effect transistor having a first source/drain region, and a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor having a second source/drain region and a gate region having first sidewall spacers. The stacked device structure further includes a frontside source/drain contact disposed on a first portion of a sidewall and a top surface of the second source/drain region, a first metal via connected to the frontside source/drain contact and to a first backside power line, and second sidewall spacers disposed on a first portion of the first metal via. The first sidewall spacers comprise a first dielectric material and the second sidewall spacers comprise a second dielectric material different than the first dielectric material.

Abstract: A semiconductor structure is provided that includes a first stacked FET cell including a second FET stacked over a first FET, and a second stacked FET cell located adjacent to the first stacked FET cell and including a fourth FET stacked over a third FET. The structure further includes a first backside source/drain contact structure located beneath the first stacked FET cell and contacting a source/drain region of the first FET, a second backside source/drain contact structure located beneath the second stacked FET cell and contacting a source/drain region of the third FET, and an angled cut region laterally separating the first backside source/drain contact structure from the second backside source/drain contact structure.

Abstract: A semiconductor IC device includes a conductive through device connection. The connection may be located within a double diffusion break (DDB) region that separates active regions. The connection may include a faux S/D region between a frontside contact and a backside contact. The semiconductor IC device may further include a first and/or second diffusion break isolation rail. The connection may be between the first and second diffusion break isolation rails. The connection location within the DDB region may resultantly increase packing densities of the semiconductor IC device. Further, the connection may reduce routing complexities and resistance through the semiconductor IC device, which may improve semiconductor IC device performance. Further, the connection may utilize mirrored structure instances (e.g., frontside contact, backside contact, faux S/D region, or the like) as that are used by microdevices (e.g., transistors, or the like) within the active regions, which may decrease fabrication complexities.

Abstract: A semiconductor structure is presented including a plurality of backside supply rails, a primary rail, a first secondary rail and a second secondary rail, wherein the second secondary rail is isolated from the primary rail, and a transistor connecting the first secondary rail to the second secondary rail to supply power therebetween. The primary rail is contiguous only with the second secondary rail. A width of the first and second secondary rails is equal to a width of the primary rail. A supply voltage connection for the first and second secondary rails is provided by a via connected to the primary rail.

Abstract: A microelectronic structure including a first nanosheet transistor including a first backside metal line that has a first width as measure along a bottom surface of the first backside metal line and the first backside metal line has a second width as measure along a top surface of the first backside metal line. A second backside metal line that includes a second backside contact that is connected to the second source drain and the second backside metal line has a third width as measure along a bottom surface of the second backside metal line. The second backside metal line has a fourth width as measure along a top surface of the second backside metal line. The first width is larger than the second width and the third width is larger than the fourth width.

Abstract: An apparatus comprising a dielectric layer located between a first electrode and a second electrode and a third electrode located on the dielectric layer between the first electrode and the electrode, wherein the first electrode is separated from a first side of the third electrode by a first portion of the dielectric layer, and the second electrode is separated from a second side of the third electrode by a second portion of the dielectric layer.

Abstract: A memory cell in a backside of a wafer and methods of forming the memory cell are described. A buried metal structure can be formed through a frontside of a substrate. At least one device can be formed on the frontside of a substrate, where the at least one device can be connected to the buried metal structure in the substrate. A through silicon via (TSV) can be formed through a backside of the substrate, where the TSV can be connected to the buried metal structure. A memory cell can be formed on the backside of the substrate, where the memory cell can be connected to the TSV.

Abstract: Embodiments disclosed herein describe semiconductor devices that include semiconductor structures and methods of forming the semiconductor structures. The semiconductor structures may include an upper conductive line, a first lower conductive line laterally insulated by a first lower dielectric region and a second lower dielectric region. The semiconductor structure also includes a lower level via region above the first lower conductive line. The lower level via region includes a dielectric blocking material and a spacer material.

Abstract: A semiconductor structure including a gate contact above and in direct contact with a top surface of a gate. a backside wiring layer below a backside power delivery network. and a contact via extending between the gate contact and the backside wiring layer.

Abstract: Embodiments of present invention provide an interconnect structure. The structure includes a metal line embedded in a dielectric layer; a first via intersecting with the metal line; and a second via intersecting with the metal line, the second via being horizontally separated from the first via by a length that is less than a blech length of the metal line, where the first and the second via extend vertically at least from a top surface of the metal line to a bottom surface of the metal line and have a width that is equal to or large than a width of the metal line. One or more method of forming the same are also provided.

Abstract: A memory structure that includes a dielectric stack of a ferroelectric dielectric layer and a paraelectric dielectric layer. At least the ferroelectric dielectric layer produces a negative capacitance to amplify an applied voltage. A thickness of the ferroelectric dielectric layer and the paraelectric dielectric layer results in simultaneous breakdown of a dielectric material in each of the ferroelectric dielectric layer and the paraelectric dielectric layer for the formation of conductive filaments upon being exposed to an electric field produced by the applied voltage amplified by the negative capacitance. The memory structure also includes a first electrode at a first end of the dielectric stack, and a second electrode at a second end of the dielectric stack. The applied voltage is applied to the memory structure through at least one of the first electrode and the second electrode.

Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes an array of transistors on a semiconductor substrate, the array of transistors including a first transistor and a second transistor, the second transistor being next to the first transistor; and a metal connection between the first transistor and the second transistor, wherein the metal connection connects a first metal contact at a frontside of the array of transistors to a second metal contact at a backside of the array of transistors. A method of forming the same is also provided.

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a plurality of metal lines of a first metal level. The semiconductor interconnect structure further includes a via formed substantially offset from a centerline of a first metal line and at least partially through a first portion of the first metal line located beneath the via.