Abstract: Embodiments of present invention provide an interconnect structure. The structure includes a metal line embedded in a dielectric layer; a first via intersecting with the metal line; and a second via intersecting with the metal line, the second via being horizontally separated from the first via by a length that is less than a blech length of the metal line, where the first and the second via extend vertically at least from a top surface of the metal line to a bottom surface of the metal line and have a width that is equal to or large than a width of the metal line. One or more method of forming the same are also provided.

Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes an array of transistors on a semiconductor substrate, the array of transistors including a first transistor and a second transistor, the second transistor being next to the first transistor; and a metal connection between the first transistor and the second transistor, wherein the metal connection connects a first metal contact at a frontside of the array of transistors to a second metal contact at a backside of the array of transistors. A method of forming the same is also provided.

Abstract: A memory structure that includes a dielectric stack of a ferroelectric dielectric layer and a paraelectric dielectric layer. At least the ferroelectric dielectric layer produces a negative capacitance to amplify an applied voltage. A thickness of the ferroelectric dielectric layer and the paraelectric dielectric layer results in simultaneous breakdown of a dielectric material in each of the ferroelectric dielectric layer and the paraelectric dielectric layer for the formation of conductive filaments upon being exposed to an electric field produced by the applied voltage amplified by the negative capacitance. The memory structure also includes a first electrode at a first end of the dielectric stack, and a second electrode at a second end of the dielectric stack. The applied voltage is applied to the memory structure through at least one of the first electrode and the second electrode.

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a plurality of metal lines of a first metal level. The semiconductor interconnect structure further includes a via formed substantially offset from a centerline of a first metal line and at least partially through a first portion of the first metal line located beneath the via.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. First and second FETs are formed. A top surface of the semiconductor structure is bonded to a carrier wafer. The semiconductor structure is flipped. A MIM capacitor plane comprising first and second metal layers is formed. An ILD layer is formed on the MIM capacitor plane. A first trench is formed within the MIM capacitor plane and the ILD layer. Exposed portions of the first metal layer are recessed within the first trench. A second trench is formed within the MIM capacitor plane and the ILD layer. Exposed portions of the second metal layer are recessed. Dielectric spacers are formed in the recesses. A first backside contact is formed in the first trench and a second backside contact is formed in the second trench.

Abstract: Semiconductor devices and methods of forming the same include a first layer including lower colinear vertical transfer field effect transistors (VTFETs). At least two of the colinear first VTFETs have a first shared bottom source/drain structure. A second layer is positioned over the first layer and includes upper colinear VTFETs. At least two of the upper colinear VTFETs have a second shared bottom source/drain structure.

Abstract: A semiconductor structure is provided that includes a plurality of backside power islands, rather than backside power rails. The backside power islands are present in a first device track and a second device track. Each backside power island located in the first device track and the second device track are isolated by a first cut region, and the backside power islands that are located in the first device track are separated from the backside power islands located in the second device track by a second cut region. The second cut region is oriented perpendicular to the first cut region.

Abstract: A microelectronic structure including a plurality of nanosheet transistors. Each of the plurality of nanosheet transistors includes an active gate located around a plurality of active channel layers and each of the plurality of nanosheet transistors includes a source/drain region have a first length. The first length is measured perpendicular to a gate direction of the plurality of nanosheet transistors. A power via located between a first dummy device and a second dummy device and the power via has second length. The second length is measured perpendicular to a gate direction of the plurality of nanosheet transistors. The second length is larger than the first length.

Abstract: A semiconductor structure includes a first plurality of backside power rail interconnects located within a first cell height region of a substrate. A second plurality of backside power rail interconnects are located within a second cell height region of the substrate. A first isolation region is located between the first cell height region of the substrate and the second cell height region of the substrate. The first isolation region electrically separates the first cell height region and the second cell height region. A second isolation region is located between adjacent power rail interconnects of the first plurality of backside power rail interconnects and between adjacent power rail interconnects of the second plurality of backside power rail interconnects. The second isolation region electrically separates the adjacent power rail interconnects.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level, the metal level includes a metal strip including a notch at a side of the metal strip or a pass-through inside the metal strip, wherein the notch or the pass-through is at least partially filled with a dielectric material. The metal level further includes a conductive wiring that vertically passes through the metal strip. The conductive wiring is at least partially inside the notch or inside the pass-through and is insulated from the metal strip by the dielectric material. Methods of manufacturing the semiconductor structure are also provided.

Abstract: A semiconductor structure is presented including backside contacts with jumpers and frontside back-end-of-line (BEOL) components electrically connected to the backside contacts by one or more deep via contacts. The jumpers electrically connect a plurality of source/drain (S/D) regions. At least one of the backside contacts is electrically connected to a backside power rail. At least one of the backside contacts has a first height and at least one of the backside contacts has a second height, where the second height is greater than the first height.

Abstract: One or more systems, devices, and/or methods of fabrication provided herein relate to reduced resistance between contacts and source/drain epis. According to one embodiment, a semiconductor device can comprise a source/drain region comprising a top portion, a sidewall portion and a bottom portion, a dielectric bar located adjacent to the source/drain region, and a contact in direct contact with the top portion, the sidewall portion and the bottom portion of the source/drain region and with the dielectric bar.

Abstract: A semiconductor device includes a substrate including designated source or drain (source/drain) regions. An active source/drain is in the designated source/drain regions, and a source/drain cap liner is on an upper surface of the active source/drain. The semiconductor device further includes trench silicide regions completely filed with a silicide material.

Abstract: An interconnect structure includes a first metal via disposed on a first metal line of a first metallization layer disposed in a dielectric layer, a first liner layer disposed on the dielectric layer, and a second metallization layer containing a first metal line disposed on the first liner layer and the first metal via.

Abstract: A semiconductor structure is presented including a first level of interconnect wiring separated into a first interconnect wiring segment and a second interconnect wiring segment, the first interconnect wiring segment defining a first line segment and the second interconnect wiring segment defining a second line segment and a second level interconnect wiring positioned orthogonally to the first level of interconnect wiring. A distalmost end of the first line segment and a distalmost end of the second line segment are separated by a spacing less than or equal to a spacing of the second level interconnect wiring defining a zero track skip.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor wafer having a first transistor and a second transistor; a first source/drain (S/D) contact of the first transistor; a second S/D contact of the second transistor; and a cut region between the first S/D contact and the second S/D contact, wherein the cut region includes a liner of a first dielectric material and a filler of a second dielectric material that is different from the first dielectric material, the liner lining at least a part of the first S/D contact and a part of the second S/D contact, and the filler being directly adjacent to the liner and between the first S/D contact and the second S/D contact. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor device includes a backside power rail, a backside ground rail, and a backside isolation rail between the backside power rail and the backside ground rail. The backside isolation rail may provide adequate electrical isolation between the backside power rail and the backside ground rail, thereby enabling the backside power rail and the backside ground rail to be located relatively near to one another. The backside isolation rail may also cure actual electrical shorts between the backside power rail and the backside ground rail.

Abstract: An integrated circuit structure includes a power supply rail formed in a backside of a semiconductor wafer. The integrated circuit structure also includes a frontside BEOL wire layer connected to the power supply rail through a gate, wherein the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer. A method of forming an integrated circuit structure includes forming a power supply rail in a backside of a semiconductor wafer, forming a gate in the semiconductor wafer, and forming a frontside BEOL wire layer connected to the power supply rail through the gate. Again, the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer.

Abstract: A semiconductor structure includes a first backside metal rail that extends across the structure and a second backside metal rail parallel and adjacent to the first backside metal rail. The first and second backside metal rails bound a first circuit row. The structure also includes a backside signal wire that interrupts the second backside metal rail; and a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail. The second and third backside metal rails bound a second circuit row. The structure also includes gate metal pitches, which extend across the structure perpendicular to the backside metal rails. The structure also includes a frontside signal wire above the gate metal pitches; and a signal via that penetrates the structure and connects the backside signal wire to the frontside signal wire.

Abstract: Embodiments of the invention provide a multi-layer integrated circuit (IC) structure that includes a cell having a cell boundary defined by a plurality of transistor-gate pitch (TGP) regions and an in-line contact region. The plurality of TGP regions include a reduced-area TGP region and non-reduced area TGP regions. The reduced-area TGP region is less than each of the non-reduced-area TGP regions. An in-line contact is within the in-line contact region and operable to electrically couple to a source or drain (S/D) region within the in-line contact region.