Abstract: A semiconductor device architecture includes a substrate and a device region including active components carried by the substrate. A plurality of tracks are on the substrate including conductive lines connecting power and signals to the active components in the device region. A first track includes a plurality of segments of a conductive line. A first segment in the first track delivers power to the device region. A second segment in the first track delivers a signal to the device region. The first segment and the second segment are arranged in the same first track.

Abstract: A semiconductor device includes a substrate and a transistor positioned on the substrate. The transistor includes transistor includes a channel region, a shared gate region, and a source and drain region. The source and drain region includes a concave outer wall includes a concave outer wall. A method of manufacturing a semiconductor device includes providing a substrate and forming a plurality of transistor gate structures on the substrate. A source and drain region are formed and positioned adjacent the plurality of transistor gate structures. A concave wall is recessed into material of the source and drain region toward a centerline of the source and drain region.

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a damascene-based interconnect. The damascene-based interconnect includes multiple metal layer Mx structures. Additionally, the semiconductor structure includes a subtractive metal patterned interconnect. The subtractive metal patterned interconnect includes multiple Vx-1 structures, multiple spacers in contact with the Vx-1 structures, and a dielectric liner. Further, the spacers and the dielectric liner prevent electrical contact between one of the Vx-1 structures and a neighboring Mx structure of the subtractive metal patterned layer.

Abstract: A semiconductor device includes a substrate and a plurality of stacked transistors positioned on the substrate. The transistors include a gate region and a source and drain proximate the gate region. The source and drain includes an overall region and an active region. A thickness of the active region is less than a thickness of the overall region.

Abstract: An interconnect structure includes a first via metallization layer having at least a first metal via, a second via metallization layer having at least a second metal via, and a first metallization layer disposed between the first via metallization layer and the second via metallization layer, the first metallization layer comprising a first metal line and a second metal line. The first metal via is disposed on the first metal line and the second metal via is disposed on the second metal line. The second metal via is in an overlapping configuration with the first metal via.

Abstract: A microelectronic structure includes a first row of stack nano devices that includes a plurality of a first stacked nano FET devices and a second row of stack nano devices that includes a plurality of a second stacked nano FET devices. Each of the plurality of first nano stacked FET devices and each of the plurality of second stacked FET devices includes an upper stack transistor and a lower stack transistor. A gate cut located between the first row of stacked nano devices and the second row stacked nano devices. An interconnect located within gate cut. The interconnect is connected to a source/drain of one of the lower stacked transistors and the interconnect includes a non-uniform backside surface.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a device layer having a frontside and a backside and including a transistor that includes a source/drain region at the backside of the device layer; a first and a second backside metal line with the source/drain region at least partially overlapping vertically with the first backside metal line and not overlapping vertically with the second backside metal line; and a backside local interconnect that conductively connects the source/drain region of the transistor with the second backside metal line, where the backside local interconnect includes a first portion and a second portion, the first portion horizontally extending from an area underneath the source/drain region to an area outside the source/drain region of the transistor, the second portion vertically connecting the first portion to the second backside metal line. Methods for forming the same are also provided.

Abstract: A semiconductor structure including a device layer, a back end-of-line layer, and a backside power distribution layer. The backside power distribution layer includes a first line network with having a first pitch, and a second line network having a second pitch. The second pitch is greater than the first pitch. In one example, the second pitch is at least 7 times (7×) greater than the first pitch.

Abstract: A microelectronic structure including a backside-power-distribution-network (BSDPN) connected to a backside of a device region. The BSPDN includes a plurality of first type power rails and a plurality of second type power rails located on the same level. A first power plane located on a level above the plurality of first type power rails and the plurality of second type power rails. The first power plane extends across the plurality of first type power rails and the plurality of second type power rails and the first power plane is connected to a plurality of first type power rails, but not connected to the plurality of second type power rails.

Abstract: A semiconductor interconnect structure and formation thereof. The semiconductor interconnect structure includes a subtractively formed via located on top of a lower level metal line. The subtractively formed via has a bottom portion and a top portion. The semiconductor interconnect structure further includes a selectively grown region formed onto the top portion of the subtractively formed via. A portion of the selectively grown region overhangs the bottom portion of the subtractively formed via in one or more directions.

Abstract: A semiconductor structure with a first backside metal level that has a plurality of first type of lines and at least one second type line. The first type of lines have a wider top surface than the bottom surface and have a first width. The first type of lines each connect by a first via to a second backside metal level. Each of first type of lines and the second type line connect by a second via to a through-silicon via. The second type line is narrower than the first type of lines. Each of the second type line is between adjacent first type of lines. The second type line has a top surface that is in the middle of the first type of lines, below the first type of lines, above, or level with the top surface of the first type of lines.

Abstract: A semiconductor structure includes a plurality of vertical transport field effect transistors, and an interconnect structure connected to one of respective source/drain regions of at least two vertical transport field effect transistors of the plurality of vertical transport field effect transistors and respective gate regions of the at least two vertical transport field effect transistors. The interconnect structure comprises a damascene portion, and a subtractive portion disposed on the damascene portion.

Abstract: A semiconductor structure includes a stacked device structure containing a first device and a second device over the first device in a stacked configuration. The semiconductor structure further includes a first backside contact connected to the first device and a first backside power line. The semiconductor structure further includes a second backside contact connected to the second device and a second backside power line.

Abstract: According to the embodiment of the present invention, a semiconductor device includes a first nanodevice comprised of a plurality of first transistors and a second nanodevice comprised of a plurality of second transistors. The second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. A first backside signal line and a second backside signal line are located at a cell boundary of the first nanodevice. A first gap exists between the first backside signal line and the second backside signal line.

Abstract: A semiconductor structure is provided that includes a first stacked FET cell including a second FET stacked over a first FET, and a second stacked FET cell located adjacent to the first stacked FET cell and including a fourth FET stacked over a third FET. The structure further includes a first backside source/drain contact structure located beneath the first stacked FET cell and contacting a source/drain region of the first FET, a second backside source/drain contact structure located beneath the second stacked FET cell and contacting a source/drain region of the third FET, and an angled cut region laterally separating the first backside source/drain contact structure from the second backside source/drain contact structure.

Abstract: A semiconductor structure includes a stacked device structure having a first field-effect transistor having a first source/drain region, and a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor having a second source/drain region and a gate region having first sidewall spacers. The stacked device structure further includes a frontside source/drain contact disposed on a first portion of a sidewall and a top surface of the second source/drain region, a first metal via connected to the frontside source/drain contact and to a first backside power line, and second sidewall spacers disposed on a first portion of the first metal via. The first sidewall spacers comprise a first dielectric material and the second sidewall spacers comprise a second dielectric material different than the first dielectric material.

Abstract: A semiconductor IC device includes a conductive through device connection. The connection may be located within a double diffusion break (DDB) region that separates active regions. The connection may include a faux S/D region between a frontside contact and a backside contact. The semiconductor IC device may further include a first and/or second diffusion break isolation rail. The connection may be between the first and second diffusion break isolation rails. The connection location within the DDB region may resultantly increase packing densities of the semiconductor IC device. Further, the connection may reduce routing complexities and resistance through the semiconductor IC device, which may improve semiconductor IC device performance. Further, the connection may utilize mirrored structure instances (e.g., frontside contact, backside contact, faux S/D region, or the like) as that are used by microdevices (e.g., transistors, or the like) within the active regions, which may decrease fabrication complexities.

Abstract: A semiconductor structure is presented including a plurality of backside supply rails, a primary rail, a first secondary rail and a second secondary rail, wherein the second secondary rail is isolated from the primary rail, and a transistor connecting the first secondary rail to the second secondary rail to supply power therebetween. The primary rail is contiguous only with the second secondary rail. A width of the first and second secondary rails is equal to a width of the primary rail. A supply voltage connection for the first and second secondary rails is provided by a via connected to the primary rail.

Abstract: A microelectronic structure including a first nanosheet transistor including a first backside metal line that has a first width as measure along a bottom surface of the first backside metal line and the first backside metal line has a second width as measure along a top surface of the first backside metal line. A second backside metal line that includes a second backside contact that is connected to the second source drain and the second backside metal line has a third width as measure along a bottom surface of the second backside metal line. The second backside metal line has a fourth width as measure along a top surface of the second backside metal line. The first width is larger than the second width and the third width is larger than the fourth width.

Abstract: An apparatus comprising a dielectric layer located between a first electrode and a second electrode and a third electrode located on the dielectric layer between the first electrode and the electrode, wherein the first electrode is separated from a first side of the third electrode by a first portion of the dielectric layer, and the second electrode is separated from a second side of the third electrode by a second portion of the dielectric layer.