Abstract: Systems, computer-implemented methods, and computer program products to facilitate feed-forward design of three-dimensional quantum chips are provided. According to an embodiment, a system can comprise a processor that executed computer executable components stored in memory. The computer executable components can comprise an analysis component that performs an analysis of a first layout of a first quantum chip. The computer executable components further comprise a modification component that modifies a second layout of a second quantum chip based on the analysis of the first layout.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first device layer on top of a backside back-end-of-line (BEOL) structure; a middle BEOL structure on top of the first device layer, the middle BEOL structure including multiple layers of small pitch wires and multiple layers of large pitch wires on top of the multiple layers of small pitch wires; a second device layer on top of the middle BEOL structure; a frontside BEOL structure on top of the second device layer; a first type via connection from the second device layer to the multiple layers of small pitch wires; and a second type and a third type via connection form the second device layer to the multiple layers of large pitch wires. A method of forming the same is also provided.

Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes a first cell unit including a first set of field-effect-transistors (FETs), a first cell boundary made of a first gate cut region, and a second cell boundary made of a second gate cut region; a second cell unit including a second set of FETs, a third cell boundary made of a third gate cut region, and a fourth cell boundary made of the first gate cut region; and a third cell unit including a third set of FETs, a fifth cell boundary made of the second gate cut region, and a sixth cell boundary made of a fourth gate cut region, where the first and third gate cut regions have a first width and the second and fourth gate cut region has a second width larger than the first width. A method of forming the same is also provided.

Abstract: Embodiments of present invention provide an interconnect structure. The interconnect structure includes a first metal line having a lower portion and an upper portion of different material composition, sidewalls of the lower portion of the first metal line being vertically aligned with sidewalls of the upper portion of the first metal line; a second metal line having a lower portion and an upper portion of different material composition, sidewalls of the lower portion of the second metal line being vertically aligned with sidewalls of the upper portion of the second metal line; a dielectric liner lining sidewalls of the lower and upper portions of the first metal line and sidewalls of the lower and upper portions of the second metal line; and an isolation layer between the first and second metal lines, the isolation layer including an airgap. A method of forming the same is also provided.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a plurality of lower metal lines in a first metal level; a transition via directly on top of the plurality of lower metal lines; and an upper metal line directly on top of the transition via and the upper metal line being in a second metal level and orthogonal to the plurality of lower metal lines, where at least a first lower metal line of the plurality of lower metal lines has a recessed region and a rest region, the recessed region is directly underneath the transition via and filled with a dielectric material; and isolates the rest region of the first lower metal line from the transition via. A method of manufacturing the same is also provided.

Abstract: A semiconductor structure includes an upper-level CMOS transistor layer having a plurality of upper-level N-type and P-type field effect transistors; and a frontside interconnect layer above, and interconnected with, the upper-level transistor layer. The frontside interconnect layer includes frontside power rails and frontside signal wiring, and at least three frontside interconnect layer metal levels. A lower-level CMOS transistor layer has a plurality of lower-level N-type and P-type field effect transistors; and a backside interconnect layer below, and interconnected with, the lower-level transistor layer. The backside interconnect layer includes backside power rails and backside signal wiring and at least three backside interconnect layer metal levels.

Abstract: A semiconductor structure includes an interconnect wiring level having metal lines. An insulating cut shape is disposed through a run length of one of the metal lines wherein the insulating cut shape divides the one of the metal lines into electrically isolated nets.

Abstract: A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

Abstract: A semiconductor structure extends laterally with an interconnect on one side and another interconnect on an opposing side separated by a thickness of the semiconductor structure that extends longitudinally. The semiconductor structure includes an insulating member extending laterally, a source/drain (S/D) positioned in the insulating member between the interconnects, another S/D positioned in the insulating member between the first S/D and one of the interconnects, wherein the S/Ds laps each other laterally and are offset from each other longitudinally, and a via electrically connected to the first S/D and to the aforementioned one of the interconnects.

Abstract: A semiconductor structure comprising a substrate, a first metal layer on top of the substrate, a second metal layer on top of the first metal layer and a dielectric layer adjacent to the second metal layer and at least part of the first metal layer and on top of at least part of the first metal layer. The first metal layer includes a via. The width of the second metal layer is the same as the width of the via of the first metal layer.

Abstract: A semiconductor integrated circuit (IC) device includes a backside fuse structure and a backside contact. The backside fuse structure is located within the backside of the semiconductor IC device vertically between a transistor there above and a backside back end of the line (BEOL) network. The backside fuse structure includes a fuse wire and a deep via contact that is connected to both the fuse wire and to a frontside BEOL network. The backside contact is connected to the transistor, to the backside BEOL network, and to the fuse wire. The backside fuse structure may be in a non-programmed state or a programmed state. When in a non-programmed state, an open circuit exists that prevents current flow through the fuse wire or through the backside contact.

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a stacked field effect transistor (FET) including a top FET and a bottom FET. Additionally, the semiconductor structure includes a bottom source/drain (S/D) contact jumper connection within a gate cut region. The gate cut includes a liner spacer and a dielectric fill within the first liner spacer. Additionally, the bottom S/D contact jumper is within the dielectric fill. The semiconductor structure further includes a top S/D contact fly-over over a bottom S/D contact in contact with the bottom S/D contact jumper. Additionally, the semiconductor structure includes a top S/D access metal track over the bottom S/D contact, through the top S/D contact. Further, the semiconductor structure includes a recessed gate cut liner facing the top S/D contact fly-over. Additionally, the semiconductor structure includes a non-recessed gate cut liner facing a non-fly-over top S/D contact.

Abstract: Embodiments provide metal tip-to-tip scaling for metal contacts. A structure includes a first metal line and a second metal line. The structure includes a spacer separating the first metal line from the second metal line, the spacer including a flat surface and curved tips, where the flat surface abuts the first metal line and the curved tips abut the second metal line.

Abstract: Integrated chips include first lines, formed on an underlying substrate. Spacers are formed conformally on sidewalls of the plurality of lines. Etch stop remnants are positioned on the sidewalls of the plurality of lines, between the spacers and the underlying substrate. Second lines are formed on the underlying substrate, between respective pairs of adjacent first lines.

Abstract: A semiconductor device architecture includes a substrate and a device region including active components carried by the substrate. A plurality of tracks are on the substrate including conductive lines connecting power and signals to the active components in the device region. A first track includes a plurality of segments of a conductive line. A first segment in the first track delivers power to the device region. A second segment in the first track delivers a signal to the device region. The first segment and the second segment are arranged in the same first track.

Abstract: A semiconductor device includes a substrate and a transistor positioned on the substrate. The transistor includes transistor includes a channel region, a shared gate region, and a source and drain region. The source and drain region includes a concave outer wall includes a concave outer wall. A method of manufacturing a semiconductor device includes providing a substrate and forming a plurality of transistor gate structures on the substrate. A source and drain region are formed and positioned adjacent the plurality of transistor gate structures. A concave wall is recessed into material of the source and drain region toward a centerline of the source and drain region.

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a damascene-based interconnect. The damascene-based interconnect includes multiple metal layer Mx structures. Additionally, the semiconductor structure includes a subtractive metal patterned interconnect. The subtractive metal patterned interconnect includes multiple Vx-1 structures, multiple spacers in contact with the Vx-1 structures, and a dielectric liner. Further, the spacers and the dielectric liner prevent electrical contact between one of the Vx-1 structures and a neighboring Mx structure of the subtractive metal patterned layer.

Abstract: A semiconductor device includes a substrate and a plurality of stacked transistors positioned on the substrate. The transistors include a gate region and a source and drain proximate the gate region. The source and drain includes an overall region and an active region. A thickness of the active region is less than a thickness of the overall region.

Abstract: An interconnect structure includes a first via metallization layer having at least a first metal via, a second via metallization layer having at least a second metal via, and a first metallization layer disposed between the first via metallization layer and the second via metallization layer, the first metallization layer comprising a first metal line and a second metal line. The first metal via is disposed on the first metal line and the second metal via is disposed on the second metal line. The second metal via is in an overlapping configuration with the first metal via.

Abstract: A microelectronic structure includes a first row of stack nano devices that includes a plurality of a first stacked nano FET devices and a second row of stack nano devices that includes a plurality of a second stacked nano FET devices. Each of the plurality of first nano stacked FET devices and each of the plurality of second stacked FET devices includes an upper stack transistor and a lower stack transistor. A gate cut located between the first row of stacked nano devices and the second row stacked nano devices. An interconnect located within gate cut. The interconnect is connected to a source/drain of one of the lower stacked transistors and the interconnect includes a non-uniform backside surface.