Abstract: A semiconductor device includes a backside power rail, a backside ground rail, and a backside isolation rail between the backside power rail and the backside ground rail. The backside isolation rail may provide adequate electrical isolation between the backside power rail and the backside ground rail, thereby enabling the backside power rail and the backside ground rail to be located relatively near to one another. The backside isolation rail may also cure actual electrical shorts between the backside power rail and the backside ground rail.

Abstract: An integrated circuit structure includes a power supply rail formed in a backside of a semiconductor wafer. The integrated circuit structure also includes a frontside BEOL wire layer connected to the power supply rail through a gate, wherein the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer. A method of forming an integrated circuit structure includes forming a power supply rail in a backside of a semiconductor wafer, forming a gate in the semiconductor wafer, and forming a frontside BEOL wire layer connected to the power supply rail through the gate. Again, the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer.

Abstract: A semiconductor structure includes a first backside metal rail that extends across the structure and a second backside metal rail parallel and adjacent to the first backside metal rail. The first and second backside metal rails bound a first circuit row. The structure also includes a backside signal wire that interrupts the second backside metal rail; and a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail. The second and third backside metal rails bound a second circuit row. The structure also includes gate metal pitches, which extend across the structure perpendicular to the backside metal rails. The structure also includes a frontside signal wire above the gate metal pitches; and a signal via that penetrates the structure and connects the backside signal wire to the frontside signal wire.

Abstract: Embodiments of the invention provide a multi-layer integrated circuit (IC) structure that includes a cell having a cell boundary defined by a plurality of transistor-gate pitch (TGP) regions and an in-line contact region. The plurality of TGP regions include a reduced-area TGP region and non-reduced area TGP regions. The reduced-area TGP region is less than each of the non-reduced-area TGP regions. An in-line contact is within the in-line contact region and operable to electrically couple to a source or drain (S/D) region within the in-line contact region.

Abstract: A semiconductor structure is provided that includes a resistive random access memory located on a surface of a bitline that is embedded in a shallow trench isolation structure. The structure can further include a source line that is present above the bitline or embedded in the shallow trench isolation structure.

Abstract: Integrated circuits and related logic circuits and structures employing VTFET logic devices. In particular, during middle-of-line (MOL) processing, method steps are employed for forming two-level MOL contact connector structures below first (M1) metallization level wiring formed during subsequent BEOL processing. Using damascene and subtractive metal etch techniques, respective MOL contact connector structures at two levels are formed with a second level above a first level contact. These contact connector structures at two levels below M1 metallization level can provide cross-connections to VTFET devices of logic circuits that enable increased scaling of the logic circuit designs, e.g., especially for multiplexor circuit layouts due to wiring access.

Abstract: A semiconductor structure with improved backside metal contacts includes a plurality of source/drain regions within a field effect transistor. A backside metal contact is electrically connected to at least one source/drain region of the plurality of source/drain regions. The backside metal contact includes a first taper profile. The semiconductor structure further includes a backside power rail electrically connected to the at least one source/drain region through the backside metal contact. The backside power rail includes a second taper profile that is different from the first taper profile.

Abstract: A logic cell includes a first trench capacitor disposed between and connecting a topside metal layer to a backside metal layer. The first trench capacitor includes an outer plate, connected to a first power rail on the backside metal layer, an inner plate, connected to a second power rail on backside metal layer, and an insulating layer separating the inner plate from the outer plate.

Abstract: Embodiments are disclosed for a semiconductor device including a top layer having a top vertical-transport field effect transistor (VTFET). Further, the semiconductor device includes a bottom layer disposed beneath the top layer, wherein the bottom layer includes a first bottom VTFET. Additionally, the semiconductor device includes a first frontside contact that wires, through a first backside contact and a first local interconnect, a bottom source/drain epitaxial of the first bottom VTFET to the back end of line interconnect.

Abstract: A semiconductor structure is provided that includes a MOL and/or BEOL structure for low resistance, low capacitance and design flexibility. The structure includes a first metal level including a plurality of first metal lines and a plurality of first metal vias located at same level within a first interlayer dielectric material layer, and a second metal level located above the first metal level. The second metal level includes a plurality of second metal lines and a plurality of second metal vias located at a same level within a second interlayer dielectric material layer. The first metal level is formed utilizing a damascene process and the second metal level is formed utilizing a substrative etch. A single metallization is used to provide the first and second metal levels.

Abstract: A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) structure having a source/drain (S/D) region between channel regions, primary epitaxy disposed in the S/D region and a backside contact disposed in contact with and gouging into the primary epitaxy.

Abstract: Embodiments of the invention provide a multi-layer integrated circuit (IC) structure that includes a back-end-of-line (BEOL) region at a first side of a wafer. A backside region is at a second side of the wafer that is opposite the first side of the wafer. A set of signal lines are in the BEOL region, and a set of power rails are in the backside region. The set of signal lines includes a substantially constant signal-line pitch between each signal line in the set of signal lines. The set of power rails includes a substantially varying power-rail pitch between each power rail in the set of power rails.

Abstract: One or more systems, devices, and/or methods of use provided herein relate to a semiconductor device with separate power supplies for front side and backside stacked power distribution. A semiconductor device can include one or more circuits, a first power supply, a second power supply, and a third power supply. The first power supply can be disposed on a first side of the one or more circuits. The second power supply can be disposed on the first side of the one or more circuits. Further, the third power supply can be disposed on a second side of the one or more circuits. Additionally, the first side of the one or more circuits can be opposite to the second side of the one or more circuits.

Abstract: One or more systems, devices, and/or methods of fabrication provided herein relate to semiconductor devices with discontinuous dielectric caps. According to one embodiment, a semiconductor device can comprise a first level of interconnect wiring, a second level of interconnect wiring, a third level of interconnect wiring, a discontinuous dielectric cap over the second level of interconnect wiring and a skip via connecting the first level of interconnect wiring to the third level of interconnect wiring.

Abstract: A semiconductor structure with self-aligned backside trench epitaxy includes a channel fin extending vertically from a bottom source/drain region of a field effect transistor. The bottom source/drain region includes a trench epitaxy later located underneath a bottommost surface of the channel fin. A high-k metal gate stack is disposed along sidewalls of the channel fin. The high-k metal gate is separated from the bottom source/drain region by a bottom spacer. A top source/drain region is located above a topmost surface of the channel fin. The top source/drain region is separated from the high-k metal gate by a top spacer. The semiconductor structure further includes a backside metal contact within a backside interlayer dielectric. The backside metal contact is electrically connected to, and vertically aligned with, the bottom source/drain region.

Abstract: Embodiments of the invention provide a multi-layer integrated circuit (IC) structure that includes a first transistor, a second transistor, and a contact element. The first transistor includes a first source or drain (S/D). The second transistor includes a second S/D and a gate. The contact element includes substantially horizontal features operable to connect the first S/D of the first transistor to the gate of the second transistor.

Abstract: A semiconductor structure is presented having a plurality of circuit rows, a plurality of first power rails positioned on front sides of the plurality of circuit rows, a plurality of second power rails positioned on back sides of the plurality of circuit rows, and power tap cells associated with each the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality the second power rails. In one instance, the plurality of second power rails are orthogonal to the plurality of first power rails. in another instance, the plurality of first power rails are horizontally offset from the plurality of second power rails. The one or more power vias include at least two or more different sized power vias.

Abstract: A semiconductor structure comprising a first circuit row and a second circuit row adjacent the first circuit row. The first circuit row comprises a first circuit cell and a second circuit cell, the first circuit cell having a first cell height greater than a first row height of the first circuit row, the second circuit cell having a second cell height different than the first cell height. The second circuit row comprises a third circuit cell, the third circuit cell having a third cell height less than a second row height of the second circuit row. The first circuit cell in the first circuit row is at least partially aligned with the third circuit cell in the second circuit row.

Abstract: A semiconductor structure includes a first metallization layer having a first plurality of metal containing lines, and a second metallization layer located above the first metallization layer. The second metallization layer includes a second plurality of metal containing lines. A first group of the second plurality of metal containing lines is disposed within the first metallization layer. The first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.

Abstract: A semiconductor device includes a first metallization layer; a second metallization layer formed on the first metallization layer; a third metallization layer formed on the second metallization layer; a super via extending from the first metallization layer to the third metallization layer; and an inner spacer layer formed on sidewalls of the super via from the second metallization layer to the first metallization layer.