Abstract: A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories.

Abstract: A chip assembly configuration includes an substrate with an integrated circuit on one side and a conversion mechanism on the other side. The integrated circuit and the conversion mechanism are electrically coupled by a short electrical transmission line through the substrate. Moreover, the conversion mechanism converts signals between an electrical and an optical domain, thereby allowing high-speed communication between the integrated circuit and other components and devices using optical communication (for example, in an optical fiber or an optical waveguide).

Abstract: A thermal transfer apparatus for cooling a heat-producing electronic component includes an evaporator disposed over the heat-producing electronic component and thermally coupled to the heat-producing electronic component, a plurality of heat pipes carrying a working fluid therein disposed over the evaporator and thermally coupled to the evaporator, a cold plate thermally coupled to a first end of the plurality of heat pipes, and a condenser thermally coupled to a second end of the plurality of heat pipes. The heat pipes extend over the evaporator such that the first end and the second end of the heat pipes couple to the cold plate and condenser at a location not over the heat-producing electronic component. The cold plate and the condenser are supplied with a coolant from outside the thermal transfer apparatus.

Abstract: A thermal transfer apparatus for cooling a heat-producing electronic component includes an evaporator disposed over the heat-producing electronic component and thermally coupled to the heat-producing electronic component, a plurality of heat pipes carrying a working fluid therein disposed over the evaporator and thermally coupled to the evaporator, a cold plate thermally coupled to a first end of the plurality of heat pipes, and a condenser thermally coupled to a second end of the plurality of heat pipes. The heat pipes extend over the evaporator such that the first end and the second end of the heat pipes couple to the cold plate and condenser at a location not over the heat-producing electronic component. The cold plate and the condenser are supplied with a coolant from outside the thermal transfer apparatus.

Abstract: A mechanism is disclosed for cooling electronic components of a module housed in a chassis. The chassis may be, for example, a rack or other housing, which may contain many such modules. The system comprises an external cooling system, and an internal cooling system for cooling electronic components on the module. The internal cooling system may reside on the module. The internal cooling system can be removed from the chassis to enable servicing components on the module without disconnecting any lines carrying cooling fluid in either fluid cooling system.

Abstract: A system includes electronic equipment, a device arranged to cool air using a refrigerant, the device secured to one of a top side and a bottom side of the electronic equipment, and a housing arranged to enclose the electronic equipment and the device, where the cooled air is propagated from one of the top side and the bottom side of the electronic equipment to the other one of the top side and the bottom side of the electronic equipment.

Abstract: The present invention provides a method and apparatus for invalidating a victimized entry. The apparatus comprises a directory cache adapted to store one or more cache entries, and a control unit. The control unit is adapted to determine whether it is desirable to remove a shared cache entry from the directory cache, and invalidate the shared cache entry in response to determining that it is desirable to remove the shared cache entry from the directory cache.

Abstract: A method and apparatus for booting a domain in a computer system configurable with a plurality of domains. The method includes locating one or more available boot locations on one or more local storage drives and identifying a boot location on a local storage drive. The method also includes booting the domain from the boot location on the local storage drive. The device includes a first connector and a bus bridge coupled to the first connector. A storage controller is coupled to the bus bridge. A storage device is coupled to the controller. The storage device is configured to boot a domain.

Abstract: The present invention provides a method and apparatus for dynamically configuring processor resources. The method includes processing tasks associated with at least one processor, wherein the processor comprises at least one cache memory having data stored therein. The method further includes transferring at least a portion of the data of the cache memory to another location and removing the processor from a system in response to transferring at least the portion of the data from the cache memory to another location, while the system is in operation.

Abstract: The present invention provides a method and apparatus for invalidating a victimized entry. The apparatus comprises a directory cache adapted to store one or more cache entries, and a control unit. The control unit is adapted to determine whether it is desirable to remove a shared cache entry from the directory cache, and invalidate the shared cache entry in response to determining that it is desirable to remove the shared cache entry from the directory cache.

Abstract: Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system units as domains and clusters of domains which have both software and hardware isolation from each other. Clusters can share dynamically definable ranges of memory with each other. The domain filter has software-loadable registers on the system units and in the global routers to set the parameters of the domains and clusters. The registers label individual inter-system transactions on the routers as invalid for system units not in the same domain or cluster as the originating unit.

Abstract: A direct-execution microprogrammable microprocessor system uses an emulatory microprogrammable microprocessor for direct execution of microinstructions in main memory through a microinstruction port. A microinstruction cache with a microinstruction address extension unit serving to communicate microinstructions from the main memory to the microprogrammable microprocessor. Virtual main memory accesses occur through a system multiplexer. A virtual address extension unit and a virtual address bus provide extension and redefinition of the main memory address space of the microprogrammable microprocessor. The system also uses a context switching stack cache and an expanded address translation cache with the microprogrammable microprocessor having a reduced and redefined microinstruction set with a variable microinstruction cycle.

Abstract: An electrically alterable memory cell is described which has a capacitive imbalance for causing the memory cell to assume either of its two stable states, and which uses a capacitor as a non-volatile storage element for retaining the information stored in the memory cell during power down operation. The capacitor has an alterable capacitance-voltage curve which is employed to identify the information in the bistable multivibrator just prior to loss of power. When power is returned, the capacitor causes the bistable multivibrator to assume that stable state in which it was operating at the time power was lost.

Abstract: A novel memory array is disclosed, the array utilizing a matrix of variable threshold insulated gate field effect transistor cells. The cells are comprised solely of a gate region, having nitride and oxide layers, and a source region with the output data sensed, at the source, as a change of source charge as distinguished from the prior art sensing of a change of low impedance source voltage. In operation, each cell functions as an alterable capacitor. A negative pulse applied to the gate selects the cell. Variations in stored charge at the nitride-oxide interface causes changes in the threshold voltage and effective capacitance of the cell. The source charge may then be sensed to read the stored data.

Abstract: In order to obtain a very close fit to the characteristic curve of a non-linear sensor, such as a thermocouple, a linearized clock is developed and used to increment a counter during a time period representative of the sensor output. The linearized clock is obtained by passing a precision clock signal through a first synchronous binary rate multiplier which receives rate information from an up/down counter. The up/down counter is incremented or decremented by the output from a second synchronous binary rate multiplier which receives rate information from a programmable read only memory in accordance with the segments of the sensor's characteristic curve through which the time scan may be deemed to be passing.

Abstract: Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system units as domains and clusters of domains which have both software and hardware isolation from each other. Clusters can share dynamically definable ranges of memory with each other. The domain filter has software-loadable registers on the system units and in the global routers to set the parameters of the domains and clusters. The registers label individual inter-system transactions on the routers as invalid for system units not in the same domain or cluster as the originating unit.