Abstract: Systems and articles of manufacture for execution-based license discovery and optimization include collecting multiple parameters of execution information for one or more software processes on one or more servers in an operating system, mapping the multiple parameters of collected execution information for the one or more software processes to one or more software products, determining usage of a software product in the operating system based on the mapping of the collected multiple parameters of execution information for the one or more software processes to one or more software products, and identifying one or more software product license optimization opportunities based on a comparison of the determined usage of the software product in the operating system and an indication of all installations of the software product in the operating system.

Abstract: Techniques for execution-based license discovery and optimization. A method includes collecting execution information for one or more software processes on one or more servers in an operating system, mapping the collected execution information for the one or more software processes to one or more software products, determining usage of a software product in the operating system based on the mapping of the collected execution information for the one or more software processes to one or more software products, and identifying one or more software product license optimization opportunities based on a comparison of the determined usage of the software product in the operating system and an indication of all installations of the software product in the operating system.

Abstract: Systems and articles of manufacture for execution-based license discovery and optimization include collecting execution information for one or more software processes on one or more servers in an operating system, mapping the collected execution information for the one or more software processes to one or more software products, determining usage of a software product in the operating system based on the mapping of the collected execution information for the one or more software processes to one or more software products, and identifying one or more software product license optimization opportunities based on a comparison of the determined usage of the software product in the operating system and an indication of all installations of the software product in the operating system.

Abstract: Systems and articles of manufacture for execution-based license discovery and optimization include collecting multiple parameters of execution information for one or more software processes on one or more servers in an operating system, mapping the multiple parameters of collected execution information for the one or more software processes to one or more software products, determining usage of a software product in the operating system based on the mapping of the collected multiple parameters of execution information for the one or more software processes to one or more software products, and identifying one or more software product license optimization opportunities based on a comparison of the determined usage of the software product in the operating system and an indication of all installations of the software product in the operating system.

Abstract: Systems and articles of manufacture for execution-based license discovery and optimization include collecting execution information for one or more software processes on one or more servers in an operating system, mapping the collected execution information for the one or more software processes to one or more software products, determining usage of a software product in the operating system based on the mapping of the collected execution information for the one or more software processes to one or more software products, and identifying one or more software product license optimization opportunities based on a comparison of the determined usage of the software product in the operating system and an indication of all installations of the software product in the operating system.

Abstract: Techniques, systems, and articles of manufacture for execution-based license discovery and optimization. A method includes collecting execution information for one or more software processes on one or more servers in an operating system, mapping the collected execution information for the one or more software processes to one or more software products, determining usage of a software product in the operating system based on the mapping of the collected execution information for the one or more software processes to one or more software products, and identifying one or more software product license optimization opportunities based on a comparison of the determined usage of the software product in the operating system and an indication of all installations of the software product in the operating system.

Abstract: Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

Abstract: A method in effectuating the redirection of light which is propagated within a waveguide, and which eliminates the necessity for a bending of the waveguide, or the drawbacks encountered in directional changes in propagated light involving the need for sharp curves of essentially small-sized radii, which would resultingly lead to excessive losses in light. In this connection, the method relates to the fabricating and the provision of a wire-grid polarization beam splitter within an optical waveguide, which utilizes a diblock copolymer template to formulate the wire-grid.

Abstract: Interconnect structures possessing an organosilicate glass interlayer dielectric material with minimal stoichiometeric modification and optionally an intact organic adhesion promoter for use in semiconductor devices are provided herein. The interconnect structure is capable of delivering improved device performance, functionality and reliability owing to the reduced effective dielectric constant of the stack compared with that of those conventionally employed because of the use of a sacrificial polymeric material deposited onto the dielectric and optional organic adhesion promoter during the barrier open step done prior to ashing the patterning material. This sacrificial film protects the dielectric and optional organic adhesion promoter from modification/consumption during the subsequent ashing step during which the polymeric film is removed.

Abstract: A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and plasma photoresist removal processes and performing one or more additional plasma etch processes that do not include oxygen containing species to etch the openings to depths required for forming the damascene interconnect structures and to remove any organo-silicate material damaged by the combination of plasma etch and plasma photoresist removal processes.

Abstract: Novel interconnect structures possessing a OSG or polymeric-based (90 nm and beyond BEOL technologies) in which advanced plasma processing is utilized to reduce post lithographic CD non-uniformity (“line edge roughness”) in semiconductor devices. The novel interconnect structure has enhanced liner and seed conformality and is therefore capable of delivering improved device performance, functionality and reliability.

Abstract: Prevention of damage to an interlevel dielectric (ILD) is provided by forming an opening (e.g., trench) in the ILD, and sputtering a dielectric film onto a sidewall of the opening by overetching into a layer of the dielectric below or within the ILD during forming of the opening. The re-sputtered film protects the sidewall of the opening from subsequent plasma/ash processes and seals the porous dielectric surface along the sidewall and bottom without impacting overall process throughput. A semiconductor structure resulting from the above process is also disclosed.

Abstract: A method for protecting a semiconductor device from carbon depletion type damage includes enriching an exposed surface of a porous interlevel dielectric material (ILD) with a carbon based material, and implementing a plasma based operation on the porous ILD material. The enriching of the porous ILD material reduces effects of carbon depletion as a result of the plasma based operation.

Abstract: Systems and methods are provided for building and implementing ontology-based information resources. More specifically, multi-user collaborative, semi-automatic systems and methods are provided for constructing ontology-based information resources that are shared by a community of users, wherein ontology categories evolve over time based on categorization rules that are specified by the community of users as well as categorization rules that are automatically learned from knowledge obtained as a result of multi-user interactions and categorization decisions.

Abstract: An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.

Abstract: Interconnect structures possessing an organosilicate glass based material for 90 nm and beyond BEOL technologies in which a multilayer hardmask using a line-first approach are described. The interconnect structure of the invention achieves respective improved device/interconnect performance and affords a substantial dual damascene process window owing to the non-exposure of the OSG material to resist removal plasmas and because of the alternating inorganic/organic multilayer hardmask stack. The latter feature implies that for every inorganic layer that is being etched during a specific etch step, the corresponding pattern transfer layer in the field is organic and vice-versa.

Abstract: A high ion energy and high pressure O2/CO-based plasma for ashing field photoresist material subsequent to via-level damascene processing. The optimized plasma ashing process is performed at greater than approximately 300 mT pressure and ion energy greater than approximately 500 W conditions with an oxygen partial pressure of greater than approximately 85%. The rapid ash rate of the high pressure/high ion energy process and minimal dissociation conditions (no “source” power is applied) allow minimal interaction between the interlevel dielectric and ash chemistry to achieve minimal overall sidewall modification of less than approximately 5 nm.

Abstract: Novel interconnect structures possessing a OSG or polymeric-based (90 nm and beyond BEOL technologies) in which advanced plasma processing is utilized to reduce post lithographic CD non-uniformity (“line edge roughness”) in semiconductor devices. The novel interconnect structure has enhanced liner and seed conformality and is therefore capable of delivering improved device performance, functionality and reliability.

Abstract: Novel interconnect structures possessing a dense OSG material for 90 nm and beyond BEOL technologies in which a low power density oxygen-based de-fluorination plasma process is utilized to increase NBLoK selectivity are presented. These BEOL interconnect structures are capable of delivering enhanced reliability and performance due to the reduced risk of Cu exposure and hence electromigration and stress migration related failures. The oxygen based de-fluorination process is such that the plasma conditions employed {low power density (<0.3 Wcm?2); relatively high pressure (>100 mT); negligible ion current to wafer surface (applied source frequency only)} facilitate a physical expulsion of residual fluorine present on the chamber walls, wafer surface, and within the via structure; thus, minimizing the extent of NBLoK etching that can occur subsequent to removing polymeric byproducts of via etching.

Abstract: Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.