Abstract: Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.

Abstract: Method, apparatus and system embodiments provide support for multiple SoEMT software threads on multiple SMT logical thread contexts. A sleep state mechanism maintains a current value of an element of architecture state for each physical thread. The current value corresponds to an active virtual thread currently running on the physical thread. The sleep state mechanism also maintains sleep values of the architecture state element for each inactive thread. The active and inactive values may be maintained in a cross-bar configuration. Upon a read of the architecture state element, simplified mux logic selects among the current values to provide the current value for the appropriate active thread. Upon a thread switch, control logic associated with the sleep state mechanism swaps the active state value for the current thread with the inactive state value for the new thread.

Abstract: Methods and apparatus are disclosed to control power consumption within a processor. An example apparatus disclosed herein includes logic to identify at least one instruction type and to initialize a counter value corresponding to a maximum number of instructions to be performed, the maximum number being at least partially dependent upon the identified at least one instruction type. The example apparatus also includes processing logic to be enabled or disabled based, at least in part, on the counter value.

Abstract: Method, apparatus and system embodiments provide support for multiple SoEMT software threads on multiple SMT logical thread contexts. A thread translation table maintains physical-to-virtual thread translation information in order to provide such information to structures within a processor that utilize virtual thread information. By associating a thread translation table with such structures, a processor that supports simultaneous multithreading (SMT) may be easily retrofitted to support switch-on-event multithreading on the SMT logical processors.

Abstract: A method, apparatus, and system are provided for a multi-threaded virtual state mechanism. According to one embodiment, active thread state of a first active thread is received using a virtual state mechanism, and virtual thread state is generated in accordance with the active thread state of the first active thread, and the virtual thread state corresponding to the first active thread is forwarded to state update logic.

Abstract: Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.

Abstract: Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimized cost and performance.

Abstract: Methods and apparatus are disclosed to control power consumption within a processor. An example processor disclosed herein comprises an instruction retirement unit; a first set of functional blocks to process a first set of instructions having a first instruction type; a second set of functional blocks to process a second set of instructions having a second instruction type; and a controller to enable the first set of functional blocks to process an instruction allocated to the instruction retirement unit if the type of the instruction is the first type, and to disable the first set of functional blocks after the instruction is retired by the instruction retirement unit.

Abstract: A stack pointer update technique in which the stack pointer is updated without executing micro-operations to add or subtract a stack pointer value. The stack pointer update technique is also described to reset the stack pointer to a predetermined value without executing micro-operations to add or subtract stack a stack pointer value.

Abstract: Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance.

Abstract: Disclosed herein is a method for matching dependency coordinates and an efficient apparatus for performing the dependency coordinate matching very quickly. A plurality of buffers to store instructions is set forth. Each storage location of a buffer corresponds to a particular pair of dependency coordinates. Dependency matching logic receives the dependency coordinates for a buffered instruction and scheduling information pertaining to dispatched instructions. The dependency matching logic indicates whether a dependency precludes scheduling of the corresponding buffered instruction. Dependency checking logic produces a ready signal for the buffered instruction when no such dependency is indicated by the dependency matching logic.

Abstract: A technique for sharing register resources within a microprocessor. Embodiments of the invention pertain to a register sharing technique within a microprocessor for multiple-threads of instructions that facilitates an optimal number of physical registers to be mapped to a desired number of logical registers without incurring significant hardware overhead.

Abstract: A stack pointer update technique in which the stack pointer is updated without executing micro-operations to add or subtract a stack pointer value. The stack pointer update technique is also described to reset the stack pointer to a predetermined value without executing micro-operations to add or subtract stack a stack pointer value.

Abstract: Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimized cost and performance.

Abstract: Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance.

Abstract: An apparatus, system and method for accelerating exchange (XCHG) instructions in a processor using a register alias table (RAT) data array and a content addressable memory (CAM) to handle register renaming. The RAT has at least one read port, at least one write port, and a plurality of address entries. The CAM has at least one read address, at least one write address, and a plurality of swap addresses. A plurality of logical register numbers are used as CAM input addresses to the RAT, and the operation of the CAM is completed in a first phase and a second phase of a clock cycle. The logical register numbers that match a pair of input swap addresses are interchanged.

Abstract: Disclosed herein is a method for matching dependency coordinates and an efficient apparatus for performing the dependency coordinate matching very quickly. A plurality of buffers to store instructions is set forth. Each storage location of a buffer corresponds to a particular pair of dependency coordinates. Dependency matching logic receives the dependency coordinates for a buffered instruction and scheduling information pertaining to dispatched instructions. The dependency matching logic indicates whether a dependency precludes scheduling of the corresponding buffered instruction. Dependency checking logic produces a ready signal for the buffered instruction when no such dependency is indicated by the dependency matching logic.

Abstract: The present invention is directed to a system and method for implementing a re-ordered instruction cache. In one embodiment, groups or “packets” of instructions with specific packet sizes are formed. Each of packets includes two or more positions. The two or more positions are defined such that they support one or more different types of instructions. Each of the positions are also correlated to a subset of the specialized execution units of the processor. Given a specific packet size and definitions for each of the positions, each of the instructions are re-ordered according to instruction type and loaded into the instruction cache in the new order.

Abstract: An embodiment of the present invention includes a speculative rename table (SRT), a shadow array, and an update circuit. The SRT stores mapping of frequent and infrequent registers. The frequent registers are frequently modified by instructions dispatched from a processor core. The infrequent registers are infrequently modified by the instructions. The shadow array stores shadow registers. Each of the shadow registers contains a rename state of a corresponding frequent register after a branch instruction. The update circuit transfers contents of the shadow registers to the frequent registers based on a selection condition.

Abstract: An apparatus and method for efficiently generating a zero value may be used with instruction set architectures which do not support an explicit zero reading register (r0) to speed execution. The present invention includes a physical register that reads out a value of zero when accessed, and a Zero Instruction Logic (ZIL) unit that identifies instructions that appear to be compensating for the lack of an r0 register, and modify the stream of instructions to utilize the physical register. Embodiments of the present invention may decrease the number of instructions that must be executed, and may decrease false dependencies between instructions allowing more scheduling flexibility.