Abstract: An embodiment of the present invention includes a speculative rename table (SRT), a shadow array, and an update circuit. The SRT stores mapping of frequent and infrequent registers. The frequent registers are frequently modified by instructions dispatched from a processor core. The infrequent registers are infrequently modified by the instructions. The shadow array stores shadow registers. Each of the shadow registers contains a rename state of a corresponding frequent register after a branch instruction. The update circuit transfers contents of the shadow registers to the frequent registers based on a selection condition.

Abstract: The present invention is directed to a system and method for implementing a re-ordered instruction cache. In one embodiment, groups or “packets” of instructions with specific packet sizes are formed. Each of packets includes two or more positions. The two or more positions are defined such that they support one or more different types of instructions. Each of the positions are also correlated to a subset of the specialized execution units of the processor. Given a specific packet size and definitions for each of the positions, each of the instructions are re-ordered according to instruction type and loaded into the instruction cache in the new order.

Abstract: An apparatus and method for loading instructions into a trace cache line using instruction packetization to increase the throughput of instructions through a given rename unit. The present invention uses the properties of the particular sequence of instructions to eliminate the redundant allocation of source and destination registers which may increase the number of instructions that can be processed simultaneously without increasing the size or complexity of the rename unit.

Abstract: For use in a processor having a pipeline of insufficient width to convey all operands of a given multiple-operand instruction concurrently, a system for, and method of, processing the multiple-operand instruction. In one embodiment, the system includes: (1) node creation circuitry that creates at least first and second nodes for the multiple-operand instruction, the first node being empty and containing at least one of the operands and (2) node transmission circuitry, coupled to the node creation circuitry, that transmits the first and second nodes sequentially through the pipeline. All the operands are subsequently concurrently available within an execution stage of the pipeline for execution of the multiple-operand instruction.

Abstract: For use in a processor having a result bus of insufficient width to convey all results of a given multiple-result instruction concurrently, a system for, and method of, writing back the results of the multiple-result instruction. In one embodiment, the system includes: (1) multi-result node creation circuitry that creates a multi-result node having at least first and second results for the multiple-result instruction and (2) node transmission circuitry, coupled to the multi-result node creation circuitry, that transmits the first and second results of said multi-result node sequentially over the result bus.

Abstract: A data processor (40) keeps track of misses to a cache (71) so that multiple misses within the same cache line can be merged or folded at reload time. A load/store unit (60) includes a completed store queue (61) for presenting store requests to the cache (71) in order. If a store request misses in the cache (71), the completed store queue (61) requests the cache line from a lower-level memory system (90) and thereafter inactivates the store request. When a reload cache line is received, the completed store queue (61) compares the reload address to all entries. If at least one address matches the reload address, one entry's data is merged with the cache line prior to storage in the cache (71). Other matching entries become active and are allowed to reaccess the cache (71). A miss queue (80) coupled between the load/store unit (60) and the lower-level memory system (90) implements reload folding to improve efficiency.

Abstract: A data processor (10) has a load/store unit (28) that executes store-to-shared-data instructions before it exclusively owns the data designated by the instruction. Later, a bus interface unit (12) performs a snoop transaction to obtain exclusive ownership of the data. If data processor successfully obtains such ownership, then the data processor correctly and quickly executed the instruction with no further action required. If the data processor can not obtain ownership of the data, then data processor re-executes the instruction in the same time as if it had not acted speculatively.

Abstract: A CAM system (2) stores a plurality of data sets in a plurality of pairs of CAM cells (4) and RAM cells (6). The portion of a particular data set stored in one of the RAM cells is accessed by inputting a tag to CAM cells that matches the portion of the data set stored in the CAM cell associated with the particular RAM cell. CAM system incorporates a novel two-stage matchline re-coding scheme to improve performance. Each of a plurality of first stage circuits (10) receives a plurality of matchline signals from a plurality of CAM sets and a plurality of data inputs from the corresponding RAM sets. Each output of the first stage circuits is further processed by a second stage circuit (12) which generates the final data output. The CAM system avoids the use of self-timed control signals and sense amplifiers.