Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses are also provided.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses are also provided.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: Methods of operating integrated circuit devices include logically combining an output signal indicating whether an operation is being performed with the logic level of a command signal line to generate a command signal to control circuitry of the integrated circuit device having the logic level of the command signal line when the output signal indicates that the operation is not being performed, and having a particular logic level when the output signal indicates that the operation is being performed. Integrated circuit devices include a command signal management circuit to provide a logic level of a particular command signal to control circuitry of the integrated circuit device when control signals indicate a desire to allow the particular command signal, and to provide a particular logic level to the control circuitry when the control signals indicate a desire to block the particular command signal.

Abstract: Methods of operating a memory device include performing a first memory operation having an associated timing requirement; after completing the first memory operation, determining whether a timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds a length of time to perform a particular portion of a second memory operation; and performing the particular portion of the second memory operation between completion of the first memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds the length of time to perform the particular portion of the second memory operation.

Abstract: Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of memory cells each store data states representing two or more digits of data. The methods further include, in response to the increasing sense voltage reaching a particular level, initiating a transfer of data values of a particular digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells.

Abstract: Methods of operating a memory device include performing a first memory operation having an associated timing requirement; after completing the first memory operation, determining whether a timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds a length of time to perform a particular portion of a second memory operation; and performing the particular portion of the second memory operation between completion of the first memory operation and the expiration of its associated timing requirement if it is determined that the timing margin between completion of the first memory operation and expiration of its associated timing requirement exceeds the length of time to perform the particular portion of the second memory operation.

Abstract: Apparatus and methods for evaluating leakage currents of capacitances are described. Capacitances having excessive leakage currents may be disabled from use. An example apparatus includes a leakage detection circuit configured to be coupled to a capacitance block. The leakage detection circuit is configured to determine whether a leakage current of a capacitance of the capacitance block exceeds a current limit and is further configured to provide an output indicative of a status of the capacitance. A detection controller is coupled to the leakage detection circuit and a register, and the detection controller is configured to store data in the register indicative of the status of the capacitance based at least in part on the signal from the leakage detection circuit.

Abstract: Methods of operating integrated circuit devices include logically combining an output signal indicating whether an operation is being performed with the logic level of a command signal line to generate a command signal to control circuitry of the integrated circuit device having the logic level of the command signal line when the output signal indicates that the operation is not being performed, and having a particular logic level when the output signal indicates that the operation is being performed. Integrated circuit devices include a command signal management circuit to provide a logic level of a particular command signal to control circuitry of the integrated circuit device when control signals indicate a desire to allow the particular command signal, and to provide a particular logic level to the control circuitry when the control signals indicate a desire to block the particular command signal.

Abstract: Multiple segment operations having non-volatile state trackers in memory devices are disclosed. Operations are segmented in multiple segments and selectively performed to avoid violating timing requirements within a memory device. In at least one embodiment, a memory device operation is segmented into a plurality of segments and selectively performed within time frames of other memory device operations. Non-volatile state trackers maintain state values corresponding to each segment of multiple segmented operations.

Abstract: Method of operating memory including storing and/or using an identifier indicating repair of a memory cell.

Abstract: Memories, and methods of operating such memories, having a memory cell, sense circuitry having a gate, program circuitry and a decoder having a first signal line connected to the gate of the sense circuitry, a second signal line connected to the program circuitry, and an output selectively connected to the memory cell. The decoder is configured to selectively connect the output to the first signal line responsive to a first control signal and to selectively connect the output to the second signal line responsive to the first control signal and a second control signal. The sense circuitry is configured to selectively activate the gate responsive to a third control signal.

Abstract: Command signal management methods and circuits in memory devices are disclosed. Command signals are selectively passed and blocked to enforce safe operating characteristics within a memory device. In at least one embodiment, a command signal management circuit is configured to selectively block a command signal while a memory device operation is being performed. In at least one other embodiment, one or more command blocking circuits are configured to selectively pass and block one or more command signals generated by a memory access device coupled to the memory device while a memory device operation is being performed in the memory device.

Abstract: Method of operating memory including storing and/or using an identifier indicating repair of a memory cell.