Patents by Inventor Nicholas Hendrickson
Nicholas Hendrickson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150235676Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.Type: ApplicationFiled: May 4, 2015Publication date: August 20, 2015Inventors: Gerald Barkley, Nicholas Hendrickson
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Publication number: 20150221384Abstract: Methods of operating a memory device include applying an increasing sense voltage to a plurality of memory cells, wherein memory cells of the plurality of memory cells each store data states representing two or more digits of data. The methods further include, in response to the increasing sense voltage reaching a particular level, initiating a transfer of data values of a particular digit of data for each memory cell of the plurality of memory cells while continuing to apply the increasing sense voltage to the plurality of memory cells.Type: ApplicationFiled: April 14, 2015Publication date: August 6, 2015Applicant: MICRON TECHNOLOGY, INC.Inventor: Nicholas Hendrickson
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Publication number: 20150213862Abstract: Memories, and methods of operating such memories, having a memory cell, sense circuitry having a gate, program circuitry and a decoder having a first signal line connected to the gate of the sense circuitry, a second signal line connected to the program circuitry, and an output selectively connected to the memory cell. The decoder is configured to selectively connect the output to the first signal line responsive to a first control signal and to selectively connect the output to the second signal line responsive to the first control signal and a second control signal. The sense circuitry is configured to selectively activate the gate responsive to a third control signal.Type: ApplicationFiled: March 31, 2015Publication date: July 30, 2015Applicant: MICRON TECHNOLOGY, INC.Inventor: Nicholas Hendrickson
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Patent number: 9043661Abstract: Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.Type: GrantFiled: May 30, 2012Date of Patent: May 26, 2015Assignee: Micron Technology, Inc.Inventor: Nicholas Hendrickson
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Patent number: 9025407Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.Type: GrantFiled: August 11, 2014Date of Patent: May 5, 2015Assignee: Micron Technology, Inc.Inventors: Gerald Barkley, Nicholas Hendrickson
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Patent number: 9025381Abstract: Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory are disclosed. An example memory block-row decoder includes a plurality of block-row decoders, each of the block-row decoders having a decoder switch tree. Each block-row decoder is configured to bias a block select switch of the decoder switch tree with a first voltage while the block-row decoder is deselected and further configured to bias decoders switches of the decoder switch tree that are coupled to the block select switch with a second voltage while the block-row decoder is deselected, the second voltage less than the first voltage. An example method of deselecting a decoder of a memory includes providing decoder signals having different voltages to decoder switches from at least two different levels of a decoder switch tree while the decoder is deselected.Type: GrantFiled: January 7, 2014Date of Patent: May 5, 2015Assignee: Micron Technology, Inc.Inventor: Nicholas Hendrickson
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Patent number: 9019762Abstract: Methods of operating a memory device include determining whether each memory cell selected for a sense operation has any data state of a first subset of data states of a plurality of data states, wherein whether a memory cell has a data state that is a member of the first subset of data states determines a data value of a first portion of the data state of that memory cell. The methods further include initiating a transfer of the data values of the first portions of the data states of the selected memory cells and continuing the particular sense operation to sense for additional data states of the plurality of data states.Type: GrantFiled: January 6, 2014Date of Patent: April 28, 2015Assignee: Micron Technology, Inc.Inventor: Nicholas Hendrickson
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Patent number: 9007822Abstract: Decoding and decoder circuits in memory devices are disclosed. Array lines are biased or floated as memory device operations are performed in the memory device. In at least one embodiment, a decoder circuit includes complementary devices to bias array lines or float array lines in a memory device while particular memory device operations are performed.Type: GrantFiled: September 14, 2012Date of Patent: April 14, 2015Assignee: Micron Technology, Inc.Inventor: Nicholas Hendrickson
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Publication number: 20150006786Abstract: Multiple segment operations having non-volatile state trackers in memory devices are disclosed. Operations are segmented in multiple segments and selectively performed to avoid violating timing requirements within a memory device. In at least one embodiment, a memory device operation is segmented into a plurality of segments and selectively performed within time frames of other memory device operations. Non-volatile state trackers maintain state values corresponding to each segment of multiple segmented operations.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Anthony R. Cabrera, Nicholas Hendrickson, Robert Melcher
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Patent number: 8923068Abstract: A method for a low margin read operation that compares CRC codes receives known data and a CRC code generated from the known data. A CRC code is generated from data read from a memory cell at a first low margin reference voltage. The CRC code from the known data and the CRC code from the read data are compared and, if the codes do not match, a failed read operation is indicated. If the CRC codes do match, data is read from the memory cell at a second low margin reference voltage that is greater than the first low margin reference voltage. A CRC is generated from this read operation. If the two CRC codes match, the read operation is indicated as passed.Type: GrantFiled: October 30, 2012Date of Patent: December 30, 2014Assignee: Micron Technology, Inc.Inventors: Nicholas Hendrickson, Yihua Zhang
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Publication number: 20140347947Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.Type: ApplicationFiled: August 11, 2014Publication date: November 27, 2014Inventors: Gerald Barkley, Nicholas Hendrickson
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Patent number: 8804449Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.Type: GrantFiled: September 6, 2012Date of Patent: August 12, 2014Assignee: Micron Technology, Inc.Inventors: Gerald Barkley, Nicholas Hendrickson
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Publication number: 20140119128Abstract: Methods of operating a memory device include determining whether each memory cell selected for a sense operation has any data state of a first subset of data states of a plurality of data states, wherein whether a memory cell has a data state that is a member of the first subset of data states determines a data value of a first portion of the data state of that memory cell. The methods further include initiating a transfer of the data values of the first portions of the data states of the selected memory cells and continuing the particular sense operation to sense for additional data states of the plurality of data states.Type: ApplicationFiled: January 6, 2014Publication date: May 1, 2014Applicant: Micron Technology, Inc.Inventor: Nicholas HENDRICKSON
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Publication number: 20140119149Abstract: Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory are disclosed. An example memory block-row decoder includes a plurality of block-row decoders, each of the block-row decoders having a decoder switch tree. Each block-row decoder is configured to bias a block select switch of the decoder switch tree with a first voltage while the block-row decoder is deselected and further configured to bias decoders switches of the decoder switch tree that are coupled to the block select switch with a second voltage while the block-row decoder is deselected, the second voltage less than the first voltage. An example method of deselecting a decoder of a memory includes providing decoder signals having different voltages to decoder switches from at least two different levels of a decoder switch tree while the decoder is deselected.Type: ApplicationFiled: January 7, 2014Publication date: May 1, 2014Applicant: MICRON TECHNOLOGY, INC.Inventor: NICHOLAS HENDRICKSON
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Publication number: 20140119129Abstract: A method for a low margin read operation that compares CRC codes receives known data and a CRC code generated from the known data. A CRC code is generated from data read from a memory cell at a first low margin reference voltage. The CRC code from the known data and the CRC code from the read data are compared and, if the codes do not match, a failed read operation is indicated. If the CRC codes do match, data is read from the memory cell at a second low margin reference voltage that is greater than the first low margin reference voltage. A CRC is generated from this read operation. If the two CRC codes match, the read operation is indicated as passed.Type: ApplicationFiled: October 30, 2012Publication date: May 1, 2014Applicant: Micron Technology, Inc.Inventors: Nicholas Hendrickson, Yihua Zhang
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Publication number: 20140078821Abstract: Decoding and decoder circuits in memory devices are disclosed. Array lines are biased or floated as memory device operations are performed in the memory device. In at least one embodiment, a decoder circuit includes complementary devices to bias array lines or float array lines in a memory device while particular memory device operations are performed.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Inventor: Nicholas HENDRICKSON
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Publication number: 20140064010Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.Type: ApplicationFiled: September 6, 2012Publication date: March 6, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Gerald Barkley, Nicholas Hendrickson
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Patent number: 8625345Abstract: Apparatus and methods of operating memory devices are disclosed. In one such method, a first portion of the data states of memory cells are determined and transferred from a memory device while continuing to determine remaining portions of data states of the same memory cells. In at least one method, a data state of a memory cell is determined during a first sense phase and is transferred while the memory cell experiences additional sense phases to determine additional portions of the data state of the memory cell.Type: GrantFiled: July 27, 2011Date of Patent: January 7, 2014Assignee: Micron Technology, Inc.Inventor: Nicholas Hendrickson
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Patent number: 8625382Abstract: Block-row decoders, memory block-row decoders, memories, methods for deselecting a decoder of a memory and methods of selecting a block of memory are disclosed. An example memory block-row decoder includes a plurality of block-row decoders, each of the block-row decoders having a decoder switch tree. Each block-row decoder is configured to bias a block select switch of the decoder switch tree with a first voltage while the block-row decoder is deselected and further configured to bias decoders switches of the decoder switch tree that are coupled to the block select switch with a second voltage while the block-row decoder is deselected, the second voltage less than the first voltage. An example method of deselecting a decoder of a memory includes providing decoder signals having different voltages to decoder switches from at least two different levels of a decoder switch tree while the decoder is deselected.Type: GrantFiled: June 24, 2011Date of Patent: January 7, 2014Assignee: Micron Technology, Inc.Inventor: Nicholas Hendrickson
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Publication number: 20130326292Abstract: Memory devices adapted to repair single unprogrammable cells during a program operation, and to repair columns containing unprogrammable cells during a subsequent erase operation. Programming of such memory devices includes determining that a single cell is unprogrammable and repairing the single cell, and repairing a column containing the single cell responsive to a subsequent erase operation.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Inventor: Nicholas HENDRICKSON