Abstract: A photonic integrated circuit including a substrate, a plurality of oxide layers on the substrate, and various passive and active integrated optical components in the plurality of oxide layers. The integrated optical components include silicon nitride waveguides, a Pockets effect phase shifter (e.g., BaTiO3 phase shifter), a superconductive nanowire single photon detector (SNSPD), an optical isolation structure surrounding the SNSPD, a single photon generator, a thermal isolation structure, a heater, a temperature sensor, a photodiode for data communication (e.g., a Ge photodiode), or a combination thereof.

Abstract: The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned buried power rail structures and methods of manufacture. The method includes: forming at least one fin structure of a first dimension in a substrate; forming at least one fin structure of a second dimension in the substrate; removing at least a portion of the at least one fin structure of the second dimension to form a trench; filling the trench with conductive metal to form a buried power rail structure within the trench; and forming a contact to the buried power rail structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.

Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level has a first interconnect, a second interconnect, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first interconnect adjacent to the entrance of the cavity and a second section arranged on the second interconnect adjacent to the entrance of the cavity. A second dielectric layer is formed on the first section of the first dielectric layer and the second section of the first dielectric layer. The second dielectric layer extends from the first section of the first dielectric layer to the second section of the first dielectric layer and across the entrance to the cavity to close an airgap between the first interconnect and the second interconnect.

Abstract: Semiconductor devices including skip via structures and methods of forming the skip via structure include interconnection between two interconnect levels that are separated by at least one other interconnect level, i.e., skip via to connect Mx and Mx+2 interconnect levels, wherein the intervening metallization level (MX+1) is electrically isolated from the skip via. Cap layers in the metallization levels are pre-patterned to provide openings therein generally corresponding to locations of the skip via structure prior to high aspect ratio etching to form the skip via structure.

Abstract: The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.

Abstract: An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.

Abstract: The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.

Abstract: A method of fabricating a semiconductor device structure comprising depositing a layer of material on a dielectric stack and patterning the layer of material to form a hard mask, depositing a metal layer covering the hard mask to form a metal hard mask, forming vias in the dielectric stack using the metal hard mask, removing the metal hard mask, and forming trenches in the dielectric stack using the hard mask, wherein the hard mask and the metal hard mask are used to define a line end structure separating the trenches.

Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level includes a metallization level having a first interconnect with a first top surface, a second interconnect with a second top surface, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first top surface of the first interconnect and a second section arranged on the second top surface of the second interconnect. The first section of the first dielectric layer is separated from the second section of the first dielectric layer by the entrance of the cavity. A second dielectric layer is arranged to surround the cavity and to close the entrance to the cavity in order to encapsulate an airgap inside the cavity.

Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level has a first interconnect, a second interconnect, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first interconnect adjacent to the entrance of the cavity and a second section arranged on the second interconnect adjacent to the entrance of the cavity. A second dielectric layer is formed on the first section of the first dielectric layer and the second section of the first dielectric layer. The second dielectric layer extends from the first section of the first dielectric layer to the second section of the first dielectric layer and across the entrance to the cavity to close an airgap between the first interconnect and the second interconnect.

Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level includes a metallization level having a first interconnect with a first top surface, a second interconnect with a second top surface, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first top surface of the first interconnect and a second section arranged on the second top surface of the second interconnect. The first section of the first dielectric layer is separated from the second section of the first dielectric layer by the entrance of the cavity. A second dielectric layer is arranged to surround the cavity and to close the entrance to the cavity in order to encapsulate an airgap inside the cavity.

Abstract: Structures for measuring RIE lag depth of a semiconductor device, including: a first metal layer; a dielectric cap layer on top of the first metal layer; an electrical ground element formed beneath one or more portions of the dielectric cap layer and within the first metal layer, the electrical ground element being electrically grounded; and a second metal layer on top of the dielectric cap layer, the second metal layer having an array of one or more sub-arrays of metal wires, each sub-array being connected to a respective bond pad and having metal wires of a given width; wherein a distance from a bottom surface of the array of metal wires to a top surface of the dielectric cap layer is indicative of RIE lag depth. The disclosure also relates to methods and systems for measuring RIE lag depth and identifying the existence of an electrical short of a semiconductor device.

Abstract: An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.

Abstract: The disclosure is directed to methods of identifying a space within an integrated circuit structure as a mandrel space or a non-mandrel space. One method may include: identifying a space between freestanding spacers as being one of: a former mandrel space created by removal of a mandrel from between the freestanding spacers or a non-mandrel space between adjacent mandrels prior to removal of the mandrel, based on a line width roughness of the space, wherein the line width roughness represents a deviation of a width of the space from a centerline axis along a length of the space.

Abstract: Semiconductor devices including skip via structures and methods of forming the skip via structure include interconnection between two interconnect levels that are separated by at least one other interconnect level, i.e., skip via to connect Mx and Mx+2 interconnect levels, wherein the intervening metallization level (MX+1) is electrically isolated from the skip via. Cap layers in the metallization levels are pre-patterned to provide openings therein generally corresponding to locations of the skip via structure prior to high aspect ratio etching to form the skip via structure.

Abstract: The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.

Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.