Abstract: One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.

Abstract: In one example, the method includes forming a hard mask layer above a semiconducting substrate, forming a patterned spacer mask layer above the hard mask layer, wherein the patterned spacer mask layer is comprised of a plurality of first spacers, second spacers and third spacers, and performing a first etching process on the hard mask layer through the patterned spacer mask layer to define a patterned hard mask layer. The method also includes performing a second etching process through the patterned hard mask layer to define a plurality of first fins, second fins and third fins in the substrate, wherein the first fins have a width that corresponds approximately to a width of the first spacers, the second fins have a width that corresponds approximately to a width of the second spacers, and the third fins have a width that corresponds approximately to a width of the third spacers.

Abstract: One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.

Abstract: One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin.

Abstract: One illustrative method disclosed herein involves performing a first etching process through a patterned hard mask layer to define a plurality of spaced-apart trenches in a substrate that defines a first portion of a fin for the device, forming a layer of insulating material in the trenches and performing a planarization process on the layer of insulating material to expose the patterned hard, performing a second etching process to remove the hard mask layer and to define a cavity within the layer of insulating material, forming a second portion of the fin within the cavity, wherein the second portion of the fin is comprised of a semiconducting material that is different than the substrate, and performing a third etching process on the layer of insulating material such that an upper surface of the insulating material is below an upper surface of the second portion of the fin.

Abstract: Disclosed herein are methods of patterning features in a structure, such as a layer of material used in forming integrated circuit devices or in a semiconducting substrate, using a multiple sidewall image transfer technique. In one example, the method includes forming a first mandrel above a structure, forming a plurality of first spacers adjacent the first mandrel, forming a plurality of second mandrels adjacent one of the first spacers, and forming a plurality of second spacers adjacent one of the second mandrels. The method also includes performing at least one etching process to selectively remove the first mandrel and the second mandrels relative to the first spacers and the second spacers and thereby define an etch mask comprised of the first spacers and the second spacer and performing at least one etching process through the etch mask on the structure to define a plurality of features in the structure.

Abstract: In one example, the method includes forming a hard mask layer above a semiconducting substrate, forming a patterned spacer mask layer above the hard mask layer, wherein the patterned spacer mask layer is comprised of a plurality of first spacers, second spacers and third spacers, and performing a first etching process on the hard mask layer through the patterned spacer mask layer to define a patterned hard mask layer. The method also includes performing a second etching process through the patterned hard mask layer to define a plurality of first fins, second fins and third fins in the substrate, wherein the first fins have a width that corresponds approximately to a width of the first spacers, the second fins have a width that corresponds approximately to a width of the second spacers, and the third fins have a width that corresponds approximately to a width of the third spacers.

Abstract: Disclosed herein are methods of patterning features in a structure, such as a layer of material used in forming integrated circuit devices or in a semiconducting substrate, using a multiple sidewall image transfer technique. In one example, the method includes forming a first mandrel above a structure, forming a plurality of first spacers adjacent the first mandrel, forming a plurality of second mandrels adjacent one of the first spacers, and forming a plurality of second spacers adjacent one of the second mandrels. The method also includes performing at least one etching process to selectively remove the first mandrel and the second mandrels relative to the first spacers and the second spacers and thereby define an etch mask comprised of the first spacers and the second spacer and performing at least one etching process through the etch mask on the structure to define a plurality of features in the structure.