Abstract: A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. The metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines. The line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. The array of metal lines includes a signal line having a continuity cut disposed across its entire line width and a power line adjacent the signal line. The power line has a line width that is greater than twice the minimum line width. The power line has a notch disposed partially across its line width. The notch is aligned with the continuity cut in a direction perpendicular to the longitudinal direction of the metal lines.

Abstract: A semiconductor cell includes a dielectric layer. An array of at least four parallel metal lines is disposed within the dielectric layer, the metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines, the line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. An overall cell height of the cell is substantially equal to an integer multiple of a plurality of cell tracks, each cell track being a minimum pitch of the cell. The minimum pitch being defined by the minimum line width plus the minimum line spacer width. The minimum pitch is equal to or less than 36 nm. Not all of the line widths are substantially equal and every other line spacer width is substantially equal.

Abstract: Devices and methods of fabricating integrated circuit devices for forming assymetric line/space with barrierless metallization are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, a dielectric matrix, and a hardmask, the dielectric matrix including a set of trenches etched into the dielectric matrix and a set of dielectric fins comprising the dielectric matrix, wherein the set of trenches and the set of dielectric fins are of equal width; damaging an inner surface of each trench of the set of trenches; etching the damaged material of the trenches removing the damaged material of the dielectric matrix; removing the hardmask; and metallizing the trenches by depositing a metal directly on the dielectric matrix with no barrier between the metal and the dielectric matrix after the etching. Also disclosed is an intermediate device formed by the method.

Abstract: A method includes providing a semiconductor structure having a mandrel layer and a hardmask layer disposed above a dielectric layer. A mandrel cell is patterned into the mandrel layer. An opening is etched into the hardmask layer. The opening is self-aligned with a sidewall of the mandrel. A refill layer is disposed over the structure and recessed down to a level that is below a top surface of the hardmask layer to form an opening plug that covers a bottom of the opening. The mandrel cell is utilized to form a metal line cell into the dielectric layer, the metal line cell having metal lines and a minimum line cell pitch. The opening plug is utilized to form a continuity cut in a metal line of the metal line cell. The continuity cut has a length that is larger than the minimum line cell pitch.

Abstract: A semiconductor cell includes a dielectric layer. An array of at least four parallel metal lines is disposed within the dielectric layer, the metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines, the line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. An overall cell height of the cell is substantially equal to an integer multiple of a plurality of cell tracks, each cell track being a minimum pitch of the cell. The minimum pitch being defined by the minimum line width plus the minimum line spacer width. The minimum pitch is equal to or less than 36 nm. Not all of the line widths are substantially equal and every other line spacer width is substantially equal.

Abstract: A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. The metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines. The line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. The array of metal lines includes a signal line having a continuity cut disposed across its entire line width and a power line adjacent the signal line. The power line has a line width that is greater than twice the minimum line width. The power line has a notch disposed partially across its line width. The notch is aligned with the continuity cut in a direction perpendicular to the longitudinal direction of the metal lines.

Abstract: A method includes providing a semiconductor structure having a mandrel layer and a hardmask layer disposed above a dielectric layer. A mandrel cell is patterned into the mandrel layer. An opening is etched into the hardmask layer. The opening is self-aligned with a sidewall of the mandrel. A refill layer is disposed over the structure and recessed down to a level that is below a top surface of the hardmask layer to form an opening plug that covers a bottom of the opening. The mandrel cell is utilized to form a metal line cell into the dielectric layer, the metal line cell having metal lines and a minimum line cell pitch. The opening plug is utilized to form a continuity cut in a metal line of the metal line cell. The continuity cut has a length that is larger than the minimum line cell pitch.

Abstract: A semiconductor cell includes a dielectric layer. An array of parallel metal lines is disposed in a longitudinal direction within the dielectric layer. The metal lines having line widths that are substantially equal to or greater than a predetermined minimum line width. Line spacers are disposed between the metal lines. The line spacers having line spacer widths that are substantially equal to or greater than a predetermined minimum line spacer width. The array of metal lines includes a signal line having a continuity cut disposed across its entire line width and a power line adjacent the signal line. The power line has a line width that is greater than twice the minimum line width. The power line has a notch disposed partially across its line width. The notch is aligned with the continuity cut in a direction perpendicular to the longitudinal direction of the metal lines.

Abstract: Devices and methods of fabricating integrated circuit devices for forming assymetric line/space with barrierless metallization are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, a dielectric matrix, and a hardmask, the dielectric matrix including a set of trenches etched into the dielectric matrix and a set of dielectric fins comprising the dielectric matrix, wherein the set of trenches and the set of dielectric fins are of equal width; damaging an inner surface of each trench of the set of trenches; etching the damaged material of the trenches removing the damaged material of the dielectric matrix; removing the hardmask; and metallizing the trenches by depositing a metal directly on the dielectric matrix with no barrier between the metal and the dielectric matrix after the etching. Also disclosed is an intermediate device formed by the method.

Abstract: A method includes patterning a 1st mandrel cell into a 1st mandrel layer disposed above a dielectric layer of a semiconductor structure. The 1st mandrel cell has 1st mandrels, 1st mandrel spaces and a mandrel cell pitch. A 2nd mandrel cell is patterned into a 2nd mandrel layer disposed above the 1st mandrel layer. The 2nd mandrel cell has 2nd mandrels, 2nd mandrel spaces, and the mandrel cell pitch. The 1st and 2nd mandrel cells are utilized to form metal line cells into the dielectric layer. The metal line cells have metal lines, spaces between the metal lines and a line cell pitch. The line cell pitch is equal to the mandrel cell pitch when the metal lines of the metal line cells are an even number. The line cell pitch is equal to half the mandrel cell pitch when the metal lines of the metal line cells are an odd number.

Abstract: A semiconductor cell includes a substrate and an array of at least five substantially parallel fins having substantially equal fin widths disposed on the substrate. The array includes a predetermined minimum spacing distance between at least one pair of adjacent fins within the array. The array has a first n-type fin for an n-type semiconductor device, and a first p-type fin for a p-type semiconductor device. The first p-type fin is disposed adjacent the first n-type fin and spaced a predetermined first n-to-p distance apart from the first n-type fin. The first n-to-p distance is greater than the minimum spacing distance and less than the sum of the fin width plus twice the minimum spacing distance.

Abstract: A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation.

Abstract: A method can include performing an etching process to define a fin trench having a first depth, the first depth being less that a target height of fin. A method can also include forming a layer to protect sidewalls defining the fin trench. A method can also include performing a second etching process to increase a depth of fin trench.

Abstract: A method can include performing an etching process to define a fin trench having a first depth, the first depth being less that a target height of fin. A method can also include forming a layer to protect sidewalls defining the fin trench. A method can also include performing a second etching process to increase a depth of fin trench.

Abstract: A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation.

Abstract: A nanowire device is disclosed that includes first and second nanowires, a gate structure positioned around a portion of the first and second nanowires and a phase change material surrounding at least a portion of the first nanowire in the source/drain regions of the device but not surrounding the second nanowire in the source/drain regions.

Abstract: A nanowire device is disclosed that includes first and second nanowires, a gate structure positioned around a portion of the first and second nanowires and a phase change material surrounding at least a portion of the first nanowire in the source/drain regions of the device but not surrounding the second nanowire in the source/drain regions.

Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.

Abstract: A process is provided for the removal of contaminants from a semiconductor device, for example, removing contaminants from pores of an ultra-low k film. In one aspect, a method includes: providing a dielectric layer with contaminant-containing pores and exposing the dielectric layer to a supercritical fluid. The supercritical fluid can dissolve and remove the contaminants. In another aspect, an intermediate semiconductor device structure is provided that contains a dielectric layer with contaminant-containing pores and a supercritical fluid within the pores. In another aspect, a semiconductor device structure with a dielectric layer containing uncontaminated pores is provided.