Patents by Inventor Nicolas Albert
Nicolas Albert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11894037Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.Type: GrantFiled: April 12, 2022Date of Patent: February 6, 2024Assignee: SanDisk Technologies LLCInventors: Michael Grobis, James W. Reiner, Michael Nicolas Albert Tran, Juan P. Saenz, Gerrit Jan Hemink
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Publication number: 20230386543Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Applicant: SanDisk Technologies LLCInventors: Michael Nicolas Albert Tran, Michael K. Grobis, Ward Parkinson, Nathan Franklin
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Publication number: 20230326506Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test. Techniques are also presented for initializing a cross-point array, for both first fire and cold start, by using voltage levels shifted from half-select voltage levels used in a standard memory access.Type: ApplicationFiled: April 12, 2022Publication date: October 12, 2023Applicant: SanDisk Technologies LLCInventors: Michael Grobis, James W. Reiner, Michael Nicolas Albert Tran, Juan P. Saenz, Gerrit Jan Hemink
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Publication number: 20230267981Abstract: Technology is disclosed for improving read margin in a cross-point memory array. Drive transistors pass a read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to the drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor which improves read margin. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector. Reducing Ihold of the threshold switching selector improves read margin.Type: ApplicationFiled: February 22, 2022Publication date: August 24, 2023Applicant: SanDisk Technologies LLCInventors: Ward Parkinson, James O'Toole, Thomas Trent, Nathan Franklin, Michael Grobis, James W. Reiner, Hans Jurgen Richter, Michael Nicolas Albert Tran
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Patent number: 11688446Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.Type: GrantFiled: June 22, 2022Date of Patent: June 27, 2023Assignee: SanDisk Technologies LLCInventors: Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin
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Patent number: 11682442Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.Type: GrantFiled: June 22, 2022Date of Patent: June 20, 2023Assignee: SanDisk Technologies LLCInventors: Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin
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Publication number: 20230101414Abstract: Technology is disclosed for a fast ECC engine for a mixed read of MRAM cells. A codeword read from MRAM cells using a referenced read is decoded using a first ECC mode. If decoding passes, results are provided to a host. If decoding fails, a self-referenced read (SRR) is performed. The data read using the SRR is decoded with a second ECC mode that is capable of correcting a greater number of bits than the first ECC mode. The second ECC mode may have a higher mis-correction rate than the first ECC mode (for a given raw bit error rate (RBER)). However, the RBER may be lower when using the second ECC mode. Therefore, the first and second ECC modes may result in about the same probability of an undetectable error (or mis-correction).Type: ApplicationFiled: December 15, 2021Publication date: March 30, 2023Applicant: SanDisk Technologies LLCInventors: Martin Hassner, Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin, Raj Ramanujan
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Publication number: 20230100600Abstract: Technology for reading reversible resistivity cells in a memory array when using a current-force read is disclosed. The memory cells are first read using a current-force referenced read. If the current-force referenced read is successful, then results of the current-force referenced read are returned. If the current-force referenced read is unsuccessful, then a current-force self-referenced read (SRR) is performed and results of the current-force SRR are returned. The current-force referenced read provides a very fast read of the memory cells and can be successful in most cases. The current-force SRR provides a more accurate read in the event that the current-force referenced read is not successful. Moreover, the current-force referenced read may use less power than the current-force SRR. In an aspect this mixed current-force read is used for MRAM cells, which are especially challenging to read.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Applicant: SanDisk Technologies LLCInventors: Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin, Raj Ramanujan
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Publication number: 20220335999Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.Type: ApplicationFiled: June 22, 2022Publication date: October 20, 2022Applicant: SanDisk Technologies LLCInventors: Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin
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Publication number: 20220335998Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.Type: ApplicationFiled: June 22, 2022Publication date: October 20, 2022Applicant: SanDisk Technologies LLCInventors: Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin
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Patent number: 11398262Abstract: Technology for limiting a voltage difference between two selected conductive lines in a cross-point array when using a forced current approach is disclosed. In one aspect, the selected word line voltage is clamped to a voltage limit while driving an access current through a region of the selected word line and through a region of the selected bit line. The access current flows through the memory cell to allow a sufficient voltage to successfully read or write the memory cell, while not placing undue stress on the memory cell. In some aspects, the maximum voltage that is permitted on the selected word line depends on the location of the selected memory cell in the cross-point memory array. This allows memory cells for which there is a larger IR drop to receive an adequate voltage, while not over-stressing memory cells for which there is a smaller IR drop.Type: GrantFiled: April 16, 2021Date of Patent: July 26, 2022Assignee: SanDisk Technologies LLCInventors: Michael Nicolas Albert Tran, Ward Parkinson, Michael Grobis, Nathan Franklin
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Publication number: 20220108759Abstract: Non-volatile memory structures for performing compute-in-memory inferencing for neural networks are presented. A memory array is formed according to a crosspoint architecture with a memory cell at each crosspoint junction. The multi-levels memory cells (MLCs) are formed of multiple of ultra-thin dielectric layers separated by metallic layers, where programming of the memory cell is done by selectively breaking down one or more of the dielectric layers by selecting the write voltage level. In an alternate set of embodiments, the memory cells are formed as anti-fuses.Type: ApplicationFiled: October 2, 2020Publication date: April 7, 2022Applicant: SanDisk Technologies LLCInventors: Michael Nicolas Albert Tran, Michael Grobis
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Publication number: 20220108158Abstract: An MRAM-based vector multiplication device, such as can be used for inferencing in a neural network, is presented that is ultralow power, low cost, and does not require special on-chip programming. A crosspoint array has an MRAM cell at each crosspoint junction and periphery array circuitry capable of supplying independent input voltages to each word line and reading current on each bit line. Vector multiplication is performed as an in-array multiplication of a vector of input voltages with matrix weight values encoded by the MRAM cell states. The MRAM cells can be individually programmed using a combination of input voltages and an external magnetic field. The external magnetic field is chosen so that a write voltage of one polarity reduces the anisotropy sufficiently to align the cell state with the external field, but is insufficient to align the cell if only half of the write voltage is applied.Type: ApplicationFiled: October 2, 2020Publication date: April 7, 2022Applicant: SanDisk Technologies LLCInventors: Michael Grobis, Michael Nicolas Albert Tran
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Patent number: 11289171Abstract: Non-volatile memory structures for performing compute-in-memory inferencing for neural networks are presented. A memory array is formed according to a crosspoint architecture with a memory cell at each crosspoint junction. The multi-levels memory cells (MLCs) are formed of multiple of ultra-thin dielectric layers separated by metallic layers, where programming of the memory cell is done by selectively breaking down one or more of the dielectric layers by selecting the write voltage level. In an alternate set of embodiments, the memory cells are formed as anti-fuses.Type: GrantFiled: October 2, 2020Date of Patent: March 29, 2022Assignee: SanDisk Technologies LLCInventors: Michael Nicolas Albert Tran, Michael Grobis
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Patent number: 11152047Abstract: A magnetic memory device contains a synthetic antiferromagnetic (SAF) structure that includes an antiferromagnetically coupled stack and a reference layer. The antiferromagnetically coupled stack contains plural multilayer stacks. Each multilayer stack contains at least one ferromagnetic material layer, a non-magnetic layer and a non-magnetic SAF spacer layer having a different composition than the non-magnetic layer.Type: GrantFiled: October 23, 2019Date of Patent: October 19, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Wonjoon Jung, Michael Nicolas Albert Tran
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Patent number: 11081174Abstract: A two-step SET pulse may be applied to a phase change material of a phase change memory cell in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.Type: GrantFiled: June 26, 2020Date of Patent: August 3, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhaoqiang Bai, Mac D. Apodaca, Michael K. Grobis, Michael Nicolas Albert Tran, Neil Leslie Robertson, Gerardo A. Bertero
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Publication number: 20210125650Abstract: A magnetic memory device contains a synthetic antiferromagnetic (SAF) structure that includes an antiferromagnetically coupled stack and a reference layer. The antiferromagnetically coupled stack contains plural multilayer stacks. Each multilayer stack contains at least one ferromagnetic material layer, a non-magnetic layer and a non-magnetic SAF spacer layer having a different composition than the non-magnetic layer.Type: ApplicationFiled: October 23, 2019Publication date: April 29, 2021Inventors: Wonjoon JUNG, Michael Nicolas Albert TRAN
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Patent number: 10868245Abstract: A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.Type: GrantFiled: June 5, 2019Date of Patent: December 15, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhaoqiang Bai, Mac Apodaca, Michael Grobis, Michael Nicolas Albert Tran, Neil Leslie Robertson, Gerardo Bertero
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Publication number: 20200388752Abstract: A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.Type: ApplicationFiled: June 5, 2019Publication date: December 10, 2020Inventors: Zhaoqiang BAI, Mac APODACA, Michael GROBIS, Michael Nicolas Albert TRAN, Neil Leslie ROBERTSON, Gerardo BERTERO
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Publication number: 20200365204Abstract: Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.Type: ApplicationFiled: June 26, 2020Publication date: November 19, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Zhaoqiang Bai, Mac D. Apodaca, Michael K. Grobis, Michael Nicolas Albert Tran, Neil Leslie Robertson, Gerardo A. Bertero