Abstract: Various embodiments of an intervertebral implant comprise a body extending longitudinally along a primary axis, a baseplate, a plurality of elongated arms having a vertebral support surface, the arms being articulated such that the implant has a folded-back position in which the arms are close to each other, and a deployed position in which the arms are moved away from each other, and expansion means between the folded-back and deployed positions, comprising at least two branches pivotably mounted relative to each other and attached to the elongated arms by guide means such that translation of the expansion means parallel to the primary axis causes pivoting of the branches and moves the arms away from each other.

Abstract: Methods for generating automations via natural language processing are performed by computing systems. Natural language input is received from a user interface, and an automation workflow is generated based on the natural language input. The automation workflow includes steps to build an automation. One or more of the steps is provided to the user interface, and a first field and a second field that each correspond to the one or more steps are populated in the user interface. The first field is populated with a parameter value based on the natural language input, and the second field is populated based on the parameter value. The automation is then enabled to be built and deployed.

Abstract: A method comprises receiving an input clock signal having a clock frequency band between a lower frequency limit value and an upper frequency limit value, dividing the clock frequency band in a set of frequency ranges having a set of frequency limit values that include the lower frequency limit value and the upper frequency limit value, comparing the frequency of the clock signal with the set of frequency limit values to produce comparison indicators having a first logic value when the measured frequency fails to exceed at least one frequency limit value and having a second logic value when the measured frequency exceeds the at least one frequency limit value, and, as a result of at least one of the logic values of comparison indicators having the second logic value, producing a global flag signal indicating that the measured frequency falls outside of a frequency range.

Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

Abstract: A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down.

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.

Abstract: In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.

Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

Abstract: An electrotechnical device for an aircraft includes a housing having a surface and a magnetic circuit formed by a stack of laminated sheets and composed of a yoke. The yoke is fixed on the surface of the housing by means of a thermal interface and has a surface. At least one low-frequency coil component is attached to at least part of the surface of the yoke by attachment means.

Abstract: The invention relates to an electromechanical device (10) for an aircraft, comprising: —a housing (12) having a radially internal surface (S12), —a magnetic circuit formed by a stack of laminated sheets and composed of an annular yoke (16), said yoke being arranged on the radially internal surface of said housing, said yoke having a radially internal surface (S16), —at least one low-frequency coil component (18), said coil component being integrated over at least part of the radially internal surface of said yoke.

Abstract: A processing system includes a reset circuit, a memory storing configuration data, and a hardware configuration circuit transmitting the configuration data to configuration data clients. The system executes a reset phase, configuration phase, and software runtime phase. First and second reset terminals are associated with first and second circuitries which are respectively associated with configuration data clients. The configuration data includes first and second mode configuration data for the first and second terminals. During the reset and configuration phase, the first circuitry activates a strong pull-down, and the second circuitry activates a weak pull-down.

Abstract: In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.

Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first memory error packet associated with a first memory; receiving, with the first buffer, a second memory error packet associated with a second memory; transmitting a first reading request for reading the first memory error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central memory error management unit (MEMU); in response to receiving the first reading request, reading the first memory error packet from the first buffer, transmitting the first memory error packet to a controller of the central MEMU, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second memory error packet.

Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.