Patents by Inventor Nicolas Chaussade

Nicolas Chaussade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090216957
    Abstract: A data processing apparatus is disclosed that comprises: at least one processor; at least one data store for storing data processed by said at least one processor; a shared data store for storing data processed by said at least one processor and at least one further device; and coherency control circuitry responsive to a write request from said at least one further device to determine if data related to an address targeted by said write request is stored in said at least one data store, and if it is forcing an eviction of said stored data from said at least one data store to said shared data store prior to performing said write to said shared data store; wherein said data is stored in said at least one data store in conjunction with an indicator indicating if said stored data is consistent with data stored in a corresponding address in a further data store, and said stored data is evicted whether said stored data is indicated as being consistent or inconsistent.
    Type: Application
    Filed: February 21, 2008
    Publication date: August 27, 2009
    Applicant: ARM Limited
    Inventors: Nicolas Chaussade, Stephane Eric Sebastien Brochier
  • Publication number: 20090210595
    Abstract: An integrated circuit 2 is provided including multiple devices 4, 6, 8, 10, 12, 14 for communicating via an interconnect 16. A sending device 18 includes a sideband signal indicating the use of a representation of a repeating data word in place of that repeating data word itself. The receiving device can then form the repeating pattern of data words in response to receipt of the representation. This reduces the bandwidth consumed upon the interconnect 16.
    Type: Application
    Filed: February 3, 2009
    Publication date: August 20, 2009
    Inventor: Nicolas Chaussade
  • Patent number: 7568072
    Abstract: A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: July 28, 2009
    Assignee: ARM Limited
    Inventors: Florent Begon, Philippe Luc, Elodie Charra, Nicolas Chaussade
  • Publication number: 20090182949
    Abstract: A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information.
    Type: Application
    Filed: March 17, 2009
    Publication date: July 16, 2009
    Inventors: Florent Begon, Philippe Luc, Elodie Charra, Nicolas Chaussade
  • Patent number: 7552285
    Abstract: A line fill method, line fill unit and data processing apparatus are disclosed. The line fill method, comprises the steps of: a) associating a line fill buffer with a unique identifier; b) initiating a line fill request to provide said line fill buffer with line fill data, said line fill request having said unique identifier associated therewith; and c) in the event that said line fill buffer is filled with said line fill data prior to said line fill data having been returned in response to said line fill request, associating said line fill buffer with a different unique identifier to enable a subsequent line fill request to be initiated. By enabling the line fill buffer to be associated with different unique identifiers, the line fill buffer can initiate a new request despite the previous request not having been completed without there being any concern that the returned data may be misallocated.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: June 23, 2009
    Assignee: ARM Limited
    Inventors: Florent Begon, Nicolas Chaussade, Elodie Charra, Philippe Luc
  • Patent number: 7533241
    Abstract: An integrated circuit 2 is provided with a cache memory 6 and a cache controller 10 coupled to the cache memory 6 via a cache memory interface 8. The cache controller supports different cache memory sizes. The cache memory 6 includes masking logic 14 responsive to cache memory size signals to form masked address values for use in accessing the cache memory 6. The cache controller 10 can be part of a processor core 4 which may be hardened in its design and yet able to cope with variable cache memory sizes since the masking logic 14 is provided within the cache memory 6 outside of the hardened periphery of the processor core 4.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: May 12, 2009
    Assignee: ARM Limited
    Inventors: Florent Begon, Vladimir Vasekin, Andrew Christophe Rose, Nicolas Chaussade
  • Patent number: 7487367
    Abstract: The present invention provides a data processing apparatus and method for managing access to a memory within the data processing apparatus. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain, said processor being operable such that when executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode. Further, a memory is provided for storing data required by the processor, and consists of secure memory for storing secure data and non-secure memory for storing non-secure data.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: February 3, 2009
    Assignee: ARM Limited
    Inventors: Lionel Belnet, Nicolas Chaussade, Simon Charles Watt, Peter Guy Middleton
  • Patent number: 7448050
    Abstract: In a data processing system using multiple operating systems, an interrupt which itself may be interrupted by a subsequent interrupt which will be serviced in a different operating system, guards itself against being overlooked when that subsequent interrupt has been handled by starting a stub interrupt handling routine in that other operating system before executing the main handling routine in the originating operating system. Thus, the stub interrupt handling routine will be recognised in the other operating system irrespective of other interrupt events which may occur and accordingly the interrupted interrupt handling may be restarted.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: November 4, 2008
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, Michael Robert Nonweiler, Dominic Hugo Symes
  • Publication number: 20080168233
    Abstract: Cache circuitry, a data processing apparatus including such cache circuitry, and a method of handling write requests within cache circuitry, are provided. The cache circuitry has a plurality of slots, with each slot arranged to store attributes associated with a pending access request. A record of identifiers that are available to associate with pending access requests is maintained, and control circuitry is responsive to an access request issued by a device to accept that access request as a pending access request by allocating one of the slots to that access request, obtaining one of said identifiers from the record to associate with that access request, and causing the attributes associated with that access request to be stored in the allocated slot along with the obtained identifier. A check procedure is performed to determine, for each pending access request, whether that access request is allowed to proceed.
    Type: Application
    Filed: January 10, 2007
    Publication date: July 10, 2008
    Applicant: ARM Limited
    Inventors: Philippe Luc, Florent Begon, Elodie Charra, Nicolas Chaussade
  • Publication number: 20080147921
    Abstract: A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configure
    Type: Application
    Filed: November 1, 2007
    Publication date: June 19, 2008
    Applicant: ARM Limited
    Inventors: Nicolas Chaussade, Pierre Michel Broyer, Phillipe Luc
  • Publication number: 20080148029
    Abstract: A data processing apparatus and method are provided for converting data values from a first endian format to a second endian format. Swizzle circuitry is provided within the data processing apparatus for receiving a block of data containing at least one data value, and for converting each data value in the block from the first endian format to the second endian format. The swizzle circuitry comprises first swizzle circuitry for performing a re-ordering operation on the block of data assuming the at least one data value contained therein is of a first predetermined size, in order to produce re-ordered data. Further, second swizzle circuitry is provided which is responsive to an indication that the at least one data value is of a size different to the first predetermined size to perform an additional re-ordering operation on the re-ordered data having regard to the size of the at least one data value in order to convert each data value to the second endian format.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 19, 2008
    Applicant: ARM Limited
    Inventors: Philippe Luc, Norbert Bernard Eugene Lataille, Florent Begon, Nicolas Chaussade
  • Patent number: 7383587
    Abstract: A data processing system includes a processor that can operate in a plurality of modes and in either a secure domain or a non-secure domain. At least one secure mode is a mode in the secure domain, and at least one non-secure mode is a mode in the non-secure domain. When the processor is executing a program in a secure mode and that program has access to secure data which is not accessible when the processor is operating in a non-secure mode, the processor is responsive to exception conditions for triggering exception processing. Specifically, the processor is responsive to a parameter specifying which of the exceptions should be handled by a secure mode exception handler executing in a secure mode and which should be handled by an exception handler executing in a mode within a current one of the secure domain and the non-secure domain when that exception occurs.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: June 3, 2008
    Assignee: Arm Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Publication number: 20080059705
    Abstract: A line fill method, line fill unit and data processing apparatus are disclosed. The line fill method, comprises the steps of: a) associating a line fill buffer with a unique identifier; b) initiating a line fill request to provide said line fill buffer with line fill data, said line fill request having said unique identifier associated therewith; and c) in the event that said line fill buffer is filled with said line fill data prior to said line fill data having been returned in response to said line fill request, associating said line fill buffer with a different unique identifier to enable a subsequent line fill request to be initiated. By enabling the line fill buffer to be associated with different unique identifiers, the line fill buffer can initiate a new request despite the previous request not having been completed without there being any concern that the returned data may be misallocated.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 6, 2008
    Applicant: ARM Limited
    Inventors: Florent Begon, Nicolas Chaussade, Elodie Charra, Philippe Luc
  • Publication number: 20080059713
    Abstract: The present invention provides a method and data processing apparatus comprising: a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic operable to transfer information associated with a first of the plurality of data entries from the cache to the information portion and to determine, with reference to the information, whether the first of the plurality of data entries should be written to a memory by examining the information, the eviction logic being further operable, if it is determined that the data entry should be written to the memory, to transfer the information from the eviction buffer to a bus coupled with the memory and to transfer data of the first of the plurality of data entries from the cache to a data portion of the eviction buffer, to transfer information associated with a second of the plurality of data entries from the cache to the associated portion of the eviction buffer such that the data stored by the data
    Type: Application
    Filed: August 31, 2006
    Publication date: March 6, 2008
    Inventors: Florent Begon, Philippe Luc, Elodie Charra, Nicolas Chaussade
  • Publication number: 20080059722
    Abstract: A data processing apparatus and method which handle data processing requests is disclosed. The data processing apparatus comprises: reception logic operable to receive, for subsequent issue, a request to perform a processing activity; response logic operable to receive an indication of whether the data processing apparatus is currently able, if the request was issued, perform the processing activity in response to that issued request; and optimisation logic operable, in the event that the response logic indicates that the data processing apparatus would be currently unable to perform the processing activities in response to the issued request, to alter pending requests received by the reception logic to improve the performance of the data processing apparatus.
    Type: Application
    Filed: August 31, 2006
    Publication date: March 6, 2008
    Applicant: ARM Limited
    Inventors: Elodie Charra, Nicolas Chaussade, Philippe Luc, Florent Begon
  • Patent number: 7325083
    Abstract: In a system supporting more than one operating system, a data processing thread executing on a first operating system may be subject to an interrupt which triggers interrupt handling on a second operating system. When that interrupt handling is completed on the second operating system, the first operating system is resumed using a return interrupt. The return interrupt specifies the data processing thread which is active on the second operating system such that an appropriate task switch or resumption may be made on the first operating system. The technique is particularly well suited to systems utilising a secure operating system and a non-secure operating system executing on the same hardware.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: January 29, 2008
    Assignee: Arm Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Brochier, David Hennah Mansell, Dominic Hugo Symes
  • Patent number: 7305712
    Abstract: There is a provided a data processing system comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; and wherein said processor is responsive to a switching request to initiate a switch between a secure mode and a non-secure mode under control of a mode switching program starting at a location specified by an exception vector associated with said switching request.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: December 4, 2007
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Patent number: 7305534
    Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: December 4, 2007
    Assignee: Arm Limited
    Inventors: Simon Charles Watt, Lionel Belnet, David Hennah Mansell, Nicolas Chaussade, Peter Guy Middleton
  • Publication number: 20070150640
    Abstract: An integrated circuit 2 is provided with a cache memory 6 and a cache controller 10 coupled to the cache memory 6 via a cache memory interface 8. The cache controller supports different cache memory sizes. The cache memory 6 includes masking logic 14 responsive to cache memory size signals to form masked address values for use in accessing the cache memory 6. The cache controller 10 can be part of a processor core 4 which may be hardened in its design and yet able to cope with variable cache memory sizes since the masking logic 14 is provided within the cache memory 6 outside of the hardened periphery of the processor core 4.
    Type: Application
    Filed: December 6, 2006
    Publication date: June 28, 2007
    Applicant: ARM LIMITED
    Inventors: Florent Begon, Vladimir Vasekin, Andrew Christophe Rose, Nicolas Chaussade
  • Patent number: 7231476
    Abstract: A processor operable to perform a plurality of functions, the processor comprising: an input port; a storage element operable to receive and to store an input signal input via the input port, the input signal comprising at least one control value; control logic operable to control at least one of the functions of the processor in dependence on the at least one control value; and access logic operable to receive an access control signal and to disable access via the input port to the at least one control value stored in the storage element in dependence upon the access control signal.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: June 12, 2007
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Luc Orion, Nicolas Chaussade