Patents by Inventor Nicolas Chaussade

Nicolas Chaussade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7124274
    Abstract: An apparatus for processing data, the apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including at least one secure mode being a mode in the secure domain; and at least one non-secure mode being a mode in the non-secure domain. When the processor is executing a program in a secure mode, the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor further includes a non-secure translation table base address register and a secure translation table base address register operable in the non-secure and secure domain, respectively, to indicate a region of memory storing either non-secure or secure domain memory mapping data defining how virtual addresses are translated to physical addresses within either the non-secure or secure domain.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: October 17, 2006
    Assignee: Arm Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, David Hennah Mansell, Michael Robert Nonweiler
  • Patent number: 7117284
    Abstract: A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A vectored interrupt controller is provided to generate an exception handler address in response to an occurrence of an except condition. The vectored interrupt controller is programmable with parameters specifying for each exception condition whether an exception handler in the secure or the non-secure domain should be triggered and an exception handler address for use if the exception occurs when in the appropriate domain. The vectored interrupt controller also includes a parameter specifying a domain switching exception handler address for use if the exception condition occurs when the processor is not in the appropriate domain.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: October 3, 2006
    Assignee: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, David Hennah Mansell, Jonathan Sean Callan
  • Publication number: 20050160210
    Abstract: There is provided an apparatus for processing data, said apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; and a vectored interrupt controller operable to generate an exception handler address for supply to said processor in response to occurrence of an exception condition in accordance with programmable parameters specifying: for each of a plurality of exception conditions, a domain value indicating whether said exception condition should trigger an exception handler in said secure domain or said non-secure domain; for each of said plurality of exception conditions, an exception handler address for use if said excepti
    Type: Application
    Filed: November 17, 2003
    Publication date: July 21, 2005
    Applicant: ARM Limited
    Inventors: Simon Watt, Christopher Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Brochier, David Mansell, Jonathan Callan
  • Publication number: 20040177261
    Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data.
    Type: Application
    Filed: November 17, 2003
    Publication date: September 9, 2004
    Inventors: Simon Charles Watt, Lionel Belnet, David Hennah Mansell, Nicolas Chaussade, Peter Guy Middleton
  • Publication number: 20040177269
    Abstract: The present invention provides a data processing apparatus and method for managing access to a memory within the data processing apparatus. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain, said processor being operable such that when executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode. Further, a memory is provided for storing data required by the processor, and consists of secure memory for storing secure data and non-secure memory for storing non-secure data.
    Type: Application
    Filed: November 17, 2003
    Publication date: September 9, 2004
    Applicant: ARM LIMITED
    Inventors: Lionel Belnet, Nicolas Chaussade, Simon Charles Watt, Peter Guy Middleton
  • Publication number: 20040163013
    Abstract: A processor operable to perform a plurality of functions, the processor comprising: an input port; a storage element operable to receive and to store an input signal input via the input port, the input signal comprising at least one control value; control logic operable to control at least one of the functions of the processor in dependence on the at least one control value; and access logic operable to receive an access control signal and to disable access via the input port to the at least one control value stored in the storage element in dependence upon the access control signal.
    Type: Application
    Filed: November 17, 2003
    Publication date: August 19, 2004
    Applicant: ARM Limited
    Inventors: Simon Charles Watt, Luc Orion, Nicolas Chaussade
  • Publication number: 20040158727
    Abstract: There is a provided a data processing system comprising:
    Type: Application
    Filed: November 17, 2003
    Publication date: August 12, 2004
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Publication number: 20040158736
    Abstract: There is a provided apparatus for processing data, said apparatus comprising:
    Type: Application
    Filed: November 17, 2003
    Publication date: August 12, 2004
    Applicant: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier
  • Publication number: 20040153672
    Abstract: There is a provided a data processing system comprising:
    Type: Application
    Filed: November 17, 2003
    Publication date: August 5, 2004
    Applicant: ARM LIMITED
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Brochier
  • Publication number: 20040153593
    Abstract: In a data processing system using multiple operating systems, an interrupt which itself may be interrupted by a subsequent interrupt which will be serviced in a different operating system, guards itself against being overlooked when that subsequent interrupt has been handled by starting a stub interrupt handling routine in that other operating system before executing the main handling routine in the originating operating system. Thus, the stub interrupt handling routine will be recognised in the other operating system irrespective of other interrupt events which may occur and accordingly the interrupted interrupt handling may be restarted.
    Type: Application
    Filed: November 17, 2003
    Publication date: August 5, 2004
    Applicant: ARM LIMITED
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, Michael Robert Nonweiler, Dominic Hugo Symes
  • Publication number: 20040153807
    Abstract: In a system supporting more than one operating system, a data processing thread executing on a first operating system may be subject to an interrupt which triggers interrupt handling on a second operating system. When that interrupt handling is completed on the second operating system, the first operating system is resumed using a return interrupt. The return interrupt specifies the data processing thread which is active on the second operating system such that an appropriate task switch or resumption may be made on the first operating system. The technique is particularly well suited to systems utilising a secure operating system and a non-secure operating system executing on the same hardware.
    Type: Application
    Filed: November 17, 2003
    Publication date: August 5, 2004
    Applicant: ARM LIMITED
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Brochier, David Hennah Mansell, Dominic Hugo Symes
  • Publication number: 20040148480
    Abstract: There is provided apparatus for processing data, said apparatus comprising:
    Type: Application
    Filed: November 17, 2003
    Publication date: July 29, 2004
    Applicant: ARM Limited
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Sebastien Brochier, David Hennah Mansell, Michael Robert Nonweiler
  • Publication number: 20040139346
    Abstract: There is a provided a data processing system comprising:
    Type: Application
    Filed: November 17, 2003
    Publication date: July 15, 2004
    Applicant: ARM LIMITED
    Inventors: Simon Charles Watt, Christopher Bentley Dornan, Luc Orion, Nicolas Chaussade, Lionel Belnet, Stephane Eric Brochier