Patents by Inventor Nicolas Daval
Nicolas Daval has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11876020Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.Type: GrantFiled: September 3, 2019Date of Patent: January 16, 2024Assignee: SOITECInventors: Walter Schwarzenbach, Ludovic Ecarnot, Nicolas Daval, Bich-Yen Nguyen, Guillaume Besnard
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Publication number: 20230386896Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.Type: ApplicationFiled: August 14, 2023Publication date: November 30, 2023Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
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Patent number: 11728207Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.Type: GrantFiled: March 19, 2021Date of Patent: August 15, 2023Assignee: SoitecInventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
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Publication number: 20220059603Abstract: A method of manufacturing a substrate for a front-facing image sensor, comprises:—providing a donor substrate comprising a semiconductor layer to be transferred,—providing a semiconductor carrier substrate,—bonding the donor substrate to the carrier substrate, an electrically insulating layer being at the bonding interface,—transferring the semiconductor layer to the carrier substrate,—implanting gaseous ions in the carrier substrate via the transferred semiconductor layer and the electrically insulating layer, and—after the implantation, epitaxially growing an additional semiconductor layer on the transferred semiconductor layer.Type: ApplicationFiled: December 23, 2019Publication date: February 24, 2022Inventors: Walter Schwarzenbach, Ludovic Ecarnot, Damien Massy, Nadia Ben Mohamed, Nicolas Daval, Christophe Girard, Christophe Maleville
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Publication number: 20210225695Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.Type: ApplicationFiled: March 19, 2021Publication date: July 22, 2021Inventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
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Publication number: 20210202326Abstract: A method for manufacturing a CFET device comprises forming a substrate of the double semi-conductor on insulator type, successively comprising, from the base to the surface thereof: a carrier substrate, a first electrically insulating layer, a first single-crystal semiconductor layer, a second electrically insulating layer and a second single-crystal semiconductor layer. Slices are formed into the substrate to the first electrically insulating layer so as to form at least one fin (F). A channel of a first transistor is formed in the first semiconductor layer and a channel of a second transistor is formed opposite the first transistor in the second semiconductor layer. Formation of the substrate of the double semi-conductor on insulator type, comprises: a first and a second step of transferring a layer and thermal processing at a temperature that is sufficiently high to smooth the first single-crystal semiconductor layer to a roughness lower than 0.1 nm RMS.Type: ApplicationFiled: September 3, 2019Publication date: July 1, 2021Inventors: Walter Schwarzenbach, Ludovic Ecarnot, Nicolas Daval, Bich-Yen Nguyen, Guillaume Besnard
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Patent number: 10957577Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.Type: GrantFiled: May 17, 2017Date of Patent: March 23, 2021Assignee: SOITECInventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
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Publication number: 20200321243Abstract: A method for fabricating a strained semiconductor-on-insulator substrate comprises bonding a donor substrate to a receiving substrate with a dielectric layer at the interface. The donor substrate comprises a monocrystalline carrier substrate, an intermediate etch-stop layer, and a monocrystalline semiconductor layer. The monocrystalline semiconductor layer is transferred from the donor substrate to the receiving substrate. Trench isolations are formed to cut a portion from a layer stack including the transferred monocrystalline semiconductor layer, the dielectric layer, and the strained semiconductor material layer. The cutting operation results in relaxation of strain in the strained semiconductor material, and in application of strain to the transferred monocrystalline semiconductor layer.Type: ApplicationFiled: May 17, 2017Publication date: October 8, 2020Applicants: Soitec, SoitecInventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
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Patent number: 10672646Abstract: A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.Type: GrantFiled: May 17, 2017Date of Patent: June 2, 2020Assignee: SoitecInventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
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Publication number: 20190181035Abstract: A method for fabricating a strained semiconductor-on-insulator substrate includes bonding a donor substrate to a receiving substrate, with a dielectric layer at the interface, and transferring a monocrystalline semiconductor layer from the donor substrate to the receiving substrate. A portion is cut from a stack formed from the transferred monocrystalline semiconductor layer from the dielectric layer and from the strained semiconductor material layer. The cutting results in the relaxation of the strain in the strained semiconductor material, and in the application of at least a part of the strain to the transferred monocrystalline semiconductor layer. The method also involves the formation, on the strained semiconductor material layer of the receiving substrate, of a dielectric bonding layer or of a bonding layer consisting of the same relaxed, or at least partially relaxed, monocrystalline material as the monocrystalline semiconductor layer of the donor substrate.Type: ApplicationFiled: May 17, 2017Publication date: June 13, 2019Applicant: SoitecInventors: Walter Schwarzenbach, Guillaume Chabanne, Nicolas Daval
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Patent number: 9768057Abstract: A method for transferring a layer from a single-crystal substrate, called a donor substrate, onto a receiver substrate, includes supplying the single-crystal donor substrate, the substrate having a notch oriented in a first direction of the crystal and a weakness region bounding the layer to be transferred, bonding of the single-crystal donor substrate onto the receiver substrate, the main surface of the donor substrate opposite to the weakness region with respect to the layer to be transferred being at the bonding interface, and detachment of the donor substrate along the weakness region. In the method, the donor substrate has, on the main surface bonded to the receiver substrate, an array of atomic steps extending essentially in a second direction of the crystal different from the first direction.Type: GrantFiled: May 19, 2016Date of Patent: September 19, 2017Assignee: SoitecInventors: Ludovic Ecarnot, Nicolas Daval, Nadia Ben Mohamed, Francois Boedt, Carole David, Isabelle Guerin
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Publication number: 20160351438Abstract: A method for transferring a layer from a single-crystal substrate, called a donor substrate, onto a receiver substrate, includes supplying the single-crystal donor substrate, the substrate having a notch oriented in a first direction of the crystal and a weakness region bounding the layer to be transferred, bonding of the single-crystal donor substrate onto the receiver substrate, the main surface of the donor substrate opposite to the weakness region with respect to the layer to be transferred being at the bonding interface, and detachment of the donor substrate along the weakness region. In the method, the donor substrate has, on the main surface bonded to the receiver substrate, an array of atomic steps extending essentially in a second direction of the crystal different from the first direction.Type: ApplicationFiled: May 19, 2016Publication date: December 1, 2016Inventors: Ludovic Ecarnot, Nicolas Daval, Nadia Ben Mohamed, Francois Boedt, Carole David, Isabell Guerin
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Patent number: 9177961Abstract: The present disclosure relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The disclosure also relates to the wafer that is produced by the new method.Type: GrantFiled: March 9, 2012Date of Patent: November 3, 2015Assignee: SOITECInventors: Nicolas Daval, Cécile Aulnette, Bich-Yen Nguyen
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Patent number: 9018678Abstract: The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.Type: GrantFiled: February 17, 2012Date of Patent: April 28, 2015Assignee: SoitecInventors: Nicolas Daval, Bich-Yen Nguyen, Cecile Aulnette, Konstantin Bourdelle
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Patent number: 8753528Abstract: The present disclosure provides a chemical etchant which is capable of removing Ge and Ge-rich SiGe alloys in a controlled manner. The chemical etchant of the present disclosure includes a mixture of a halogen-containing acid, hydrogen peroxide, and water. Water is present in the mixture in an amount of greater than 90% by volume of the entire mixture. The present disclosure also provides a method of making such a chemical etchant. The method includes mixing, in any order, a halogen-containing acid and hydrogen peroxide to provide a halogen-containing acid/hydrogen peroxide mixture, and adding water to the halogen-containing acid/hydrogen peroxide mixture. Also disclosed is a method of etching a Ge or Ge-rich SiGe alloy utilizing the chemical etchant of the present application.Type: GrantFiled: February 4, 2013Date of Patent: June 17, 2014Assignees: International Business Machines Corporation, S.O.I.TEC Silicon on Insulator TechnologiesInventors: Stephen W. Bedell, Keith E. Fogel, Nicolas Daval
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Patent number: 8367521Abstract: The present invention relates to a method of forming a SOI structure having a thin silicon layer by forming a first etch stop layer on a donor substrate, forming a second etch stop layer on the first etch stop layer, wherein the material of the second etch stop layer differs from the material of the first etch stop layer, forming a thin silicon layer on the second etch stop layer, preferably by epitaxy, and bonding the intermediate structure to a target substrate, followed by detaching the donor substrate by splitting initiated in the first etch stop layer at a weakened region and removing the remaining material of the etch stop layers to produce a final ETSOI structure. The invention also relates to the ETSOI structure produces by the described method.Type: GrantFiled: November 30, 2010Date of Patent: February 5, 2013Assignee: SoitecInventors: Nicolas Daval, Cecile Aulnette
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Publication number: 20120228672Abstract: The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, a N Field-Effect Transistor (NFET), a method for manufacturing a NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.Type: ApplicationFiled: February 17, 2012Publication date: September 13, 2012Applicant: SOITECInventors: Nicolas Daval, Bich-Yen Nguyen, Cecile Aulnette, Konstantin Bourdelle
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Publication number: 20120228689Abstract: The present invention relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The invention also relates to the wafer that is produced by the new method.Type: ApplicationFiled: March 9, 2012Publication date: September 13, 2012Applicant: SOITECInventors: Nicolas Daval, Cécile Aulnette, Bich-Yen Nguyen
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Patent number: 8183128Abstract: A method for reducing roughness of an exposed surface of an insulator layer on a substrate, by depositing an insulator layer on a substrate wherein the insulator layer includes an exposed rough surface opposite the substrate, and then smoothing the exposed rough surface of the insulator layer by exposure to a gas plasma in a chamber. The chamber contains therein a gas at a pressure of greater than 0.25 Pa but less than 30 Pa, and the gas plasma is created using a radiofrequency generator applying to the insulator layer a power density greater than 0.6 W/cm2 but less than 10 W/cm2 for at least 10 seconds to less than 200 seconds. Substrate bonding and layer transfer may be carried out subsequently to transfer the thin layer of substrate and the insulator layer to a second substrate.Type: GrantFiled: September 19, 2008Date of Patent: May 22, 2012Assignee: SoitecInventors: Nicolas Daval, Sebastien Kerdiles, Cécile Aulnette
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Publication number: 20120091100Abstract: The present disclosure provides a chemical etchant which is capable of removing Ge and Ge-rich SiGe alloys in a controlled manner. The chemical etchant of the present disclosure includes a mixture of a halogen-containing acid, hydrogen peroxide, and water. Water is present in the mixture in an amount of greater than 90% by volume of the entire mixture. The present disclosure also provides a method of making such a chemical etchant. The method includes mixing, in any order, a halogen-containing acid and hydrogen peroxide to provide a halogen-containing acid/hydrogen peroxide mixture, and adding water to the halogen-containing acid/hydrogen peroxide mixture. Also disclosed is a method of etching a Ge or Ge-rich SiGe alloy utilizing the chemical etchant of the present application.Type: ApplicationFiled: October 14, 2010Publication date: April 19, 2012Applicants: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, International Business Machines CorporationInventors: Stephen W. Bedell, Keith E. Fogel, Nicolas Daval