Abstract: The present invention relates to a power junction device including a substrate of the SiCOI type with a layer of silicon carbide (16) insulated from a solid carrier (12) by a buried layer of insulant (14), and including at least one Schottky contact between a first metal layer (40) and the surface layer of silicon carbide (16), the first metal layer (30) constituting an anode.

Abstract: The present invention provides a method of forming a structure produced from semiconductor materials with the structure having a substrate layer and an insulating layer, and the method including the steps of creating the insulating layer involving constituting an oxidizable layer on the substrate layer and oxidizing the oxidizable layer. The method includes the steps of providing a thin elemental insulating layer at a mean thickness of 20 nm or less upon a substrate layer; providing an oxidizable layer upon the insulating layer; thermally oxidizing the oxidizable layer so that the combination of the oxidized oxidizable layer and the thin elemental insulating layer provides a desired thickness of the insulating layer of the structure.

Abstract: The invention relates to a method of forming a structure comprising a removed layer taken from a donor wafer, the donor wafer including a first layer formed of Si1-xGex and a second layer of Si1-yGey on the first layer, where x and y, respectively, are in the range of 0 to 1, with x being different from y. The method includes the steps of providing a donor wafer that includes a first layer of Si1-xGex and a second layer of Si1-yGey located on the first layer, with x and y respectively, being in the range of 0 to 1, and x being different than y; implanting atomic species into the donor wafer to form a zone of weakness in the first layer; bonding the donor wafer to a receiver wafer; detaching the second layer and a portion of the first layer from the donor wafer by supplying energy to bonded wafers sufficient to cause cleavage at the zone of weakness to form an intermediate structure thereof; conducting a rapid thermal anneal of the intermediate structure at a temperature of about 1000° C.

Abstract: The invention provides a method of producing a structure of a thin layer of semiconductor material on a support substrate. The thin layer is obtained from a donor substrate and includes an upper layer of semiconductor material. The method includes forming on the upper layer a bonding layer of a material that accepts diffusion from an element of the material of the upper layer, bonding the donor substrate from the side on which the bonding layer is formed on the upper layer to the support substrate, and diffusing the element from the upper layer into the bonding layer to homogenize the concentration of the element in the bonding layer and the upper layer. The result is that the thin layer of the structure is joined by the bonding layer to the upper layer.

Abstract: A method for thermally treating a silicon germanium semiconductor layer from a donor wafer is described. An embodiment of the technique includes co-implanting atomic species into a first surface of the donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer layer, bonding the first surface of the donor wafer to a host wafer, supplying energy to detach the transfer layer from the donor wafer at the zone of weakness, and conducting a recovery operation on the transfer layer. The recovery operation is conducted after detachment but while the layer remains in contact with the donor wafer. The recovery operation includes heat treating the transfer layer for a predetermined duration at a recovery temperature that is lower than a re-adhesion temperature at which the transfer layer would re-adhere to the donor wafer, to improve the crystalline quality and the surface roughness of the transfer layer.

Abstract: A method for transferring a layer of semiconductor material from a wafer is described. The wafer includes a support substrate and an upper surface that includes a buffer layer of a material having a first lattice parameter. In an embodiment, the technique includes growing a strained layer on the buffer layer. The strained layer is made of a semiconductor material having a nominal lattice parameter that is substantially different from the first lattice parameter, and it is grown to a thickness that is sufficiently thin to avoid relaxation of the strain therein. The method also includes growing a relaxed layer on the strained layer. The relaxed layer is made of silicon and has a concentration of at least one other semiconductor material that has a nominal lattice parameter that is substantially identical to the first lattice parameter. The technique also includes providing a weakened zone in the buffer layer, and supplying energy to detach a structure at the weakened zone.

Abstract: A method for forming a structure that includes a layer that is removed from a donor wafer that has a first layer made of a semiconductor material containing germanium. The method includes the steps of forming a weakness zone in the thickness of the first layer; bonding the donor wafer to a host wafer; and supplying energy so as to weaken the donor wafer at the level of the zone of weakness. The zone of weakness is formed by subjecting the donor wafer to a co-implantation of at least two different atomic species, while the bonding is carried out by performing a thermal treatment at a temperature between 300° C. and 400° C. for a duration of from 30 minutes to four hours.

Abstract: Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface; coimplanting two different atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer; bonding the free surface of the second layer to a host wafer; and supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer.

Abstract: Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface, implanting atomic species through the free surface of the second layer to form a zone of weakness zone in the first layer, and bonding the free surface of the second layer to a host wafer. The method also includes supplying energy to detach at the zone of weakness a semiconductor structure comprising the host wafer, the second layer and a portion of the first layer, conducting a bond strengthening step on the structure after detachment at a temperature of less than about 800° C. to improve the strength of the bond between the second layer and the host wafer, and selectively etching the first layer portion to remove it from the structure and to expose a surface of the second layer.

Abstract: A method for thermally treating a semiconductor layer is described. An embodiment of the technique includes implanting atomic species into a first surface of a donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer layer, bonding the first surface of the donor wafer to a host wafer, supplying energy to detach the transfer layer from the donor wafer at the zone of weakness, and conducting a recovery operation on the transfer layer. The recovery operation is conducted after detachment but while the layer remains in contact with the donor wafer. The recovery operation includes heat treating the transfer layer for a predetermined duration at a recovery temperature that is lower than a re-adhesion temperature at which the transfer layer would re-adhere to the donor wafer, to improve the crystalline quality and the surface roughness of the transfer layer.

Abstract: A method for transferring a layer of semiconductor material from a wafer is described. The wafer includes a support substrate and an upper surface that includes a buffer layer of a material having a first lattice parameter. In an embodiment, the technique includes growing a strained layer on the buffer layer. The strained layer is made of a semiconductor material having a nominal lattice parameter that is substantially different from the first lattice parameter, and it is grown to a thickness that is sufficiently thin to avoid relaxation of the strain therein. The method also includes growing a relaxed layer on the strained layer. The relaxed layer is made of silicon and has a concentration of at least one other semiconductor material that has a nominal lattice parameter that is substantially identical to the first lattice parameter. The technique also includes providing a weakened zone in the buffer layer, and supplying energy to detach a structure at the weakened zone.

Abstract: The present invention relates to a power junction device including a substrate of the SiCOI type with a layer of silicon carbide (16) insulated from a solid carrier (12) by a buried layer of insulant (14), and including at least one Schottky contact between a first metal layer (40) and the surface layer of silicon carbide (16), the first metal layer (30) constituting an anode.

Abstract: The invention provides a method of producing a structure of a thin layer of semiconductor material on a support substrate. The thin layer is obtained from a donor substrate and includes an upper layer of semiconductor material. The method includes forming on the upper layer a bonding layer of a material that accepts diffusion from an element of the material of the upper layer, bonding the donor substrate from the side on which the bonding layer is formed on the upper layer to the support substrate, and diffusing the element from the upper layer into the bonding layer to homogenize the concentration of the element in the bonding layer and the upper layer. The result is that the thin layer of the structure is joined by the bonding layer to the upper layer.